The ASIC Design And Implementation Of High-speed DDS Base On The CORDIC Algorithm

With the rapid development of modern communication technology, the frequency synthesizer performance, as a core component of communication, raised higher and higher demands, the direct digital synthesizer (DDS) device with the output signal stability, high resolution; phase-continuous, good controllability has become a modern new type of frequency synthesizer. It is developed in recent years as a frequency synthesis of new technologies, is an all-digital frequency synthesizer, usually consists of the phase accumulator, waveform ROM, DAC and low pass filter structure,and has been widely used in the present electronic systems.The key of DDS is phase-amplitude converter structure, traditional methods are mainly used ROM look-up table method. Due to restriction of ROM capacity, the performance improvement is very limited, with the development of IC process and improvement of Real-time computing speed; therefore, using real-time calculation method-coordinate rotation computer (CORDIC) algorithm is a substitute for the look-up table ROM which is feasible in the practical application.This paper firstly discussed working principle and structure of the traditional direct frequency synthesizer, and analyzed CORDIC algorithm and implementation structure. Then designed front-end RTL code of the phase accumulator, AM multiplier, simple micro-controller and CORIDC structure of the DDS with the hardware description language (Verilog), and had been prototype verified in Altera's Cyclone series FPGA and conducted a functional simulation using Quartus2, Modelsim, Debussy software. Finally, according to ASIC design flow, using TSMC 0.18μm1P6M digital standard cell library to design, with Synopsys DC-synthesis tool to synthesize the DDS front-end RTL code into gate-level netlist, with Primetime-static timing analysis tools to analysis timing, the back-end layout tools-Astro to implement physical layout,and with Calibre-the layout verification tools to do DRC/LVS work.The design of DDS circuit has the following characteristics:1. The frequency control word is 32 bits, the phase control word is 16 bits, amplitude control word is 16 bits, and the frequency resolution is 0.05Hz, the phase resolution is 2π/216, and it can communicate with the off-chip MCU to achieve the signal frequency, phase and amplitude adjustment.2. Under the TSMC0.18μm technology, RTL front-end code can be synthesize into the DDS circuit structure which can be running under 200 MHz clock frequency.3. When implementing the layout of DDS, because there is no look-up table ROM in the layout, we do not consider the mixed signal problems, and then DDS structure has a stronger anti-jamming capability.