The Research Of CORDIC Algorithm Improvement And Its Hardware Implementation

ASIC and FPGA become the ideal platform for many special fast calculationbecause of their special hardware structure. Realizing all kinds of complicatedcalculation on these becomes a hot spot. CORDIC algorithm can decompose theelementary functions into simple addition and shift operations, which laid afoundation for hardware realization of more complicated calculations. Therefore, howto design the high performance CORDIC algorithm is becoming the focus.In the study of CORDIC algorithm, more iterative times and delay have alwaysbeen the important factors which affect the application of CORDIC algorithm. Thepaper contrapose the problem of high complexity, more iterative times and limitedconvergence rang of CORDIC algorithm, aim to do some improvements on AngleRecoding CORDIC and Scaling Free CORDIC separately. Content is as follows:Contraposing the problem of high complexity of angle selection function ofAngle Recoding CORDIC, the paper proposes a Modified Angle Recoding CORDICafter analyzing the principium of angle selection function. Combined with the parallelcharacteristics of FPGA and ASIC, the new algorithm uses the renumbering schemeand the relationship between the index of constant angle and the highest ‘1’ bitposition to find the constant angle which is the nearest to the margin-angle. Thesenovel improvement schemes reduce the cost of additions and comparators, and at thesame time, decrease the complexity and latency.Contraposing the problem of more iterative times and limited co nvergence range,which greatly affect the computational accuracy, the paper propose a Double-stepScaling Free CORDIC after analyzing the characteristic of Scaling Free CORDIC.Combined with the symmetry of circumference, the new algorithm uses thedouble-step scheme to reduce the iterative times, and use the domain foldingtechnology to expand the convergence range to the entire circumference. Thecomputational accuracy is also increased because that the merger of two iterationsdecreases the roundness operations.In order to verify the above algorithm, the paper realizes the Modified AngleRecoding CORDIC and the Double-step Scaling Free CORDIC respectively based onVerilog hardware description language, and do some comparative analysis from theaspects of calculation accuracy, area consumption, iteration times as well as delay. The experimental results show the improvement schemes are very efficient.