Research And Implementation Of DDS Technology Based On CORDIC Algorithm

In recent decades, both theoretical and practical progress has been made in direct digital frequency synthesis techniques. Because of the short frequency switching time, the high frequency resolution, the continuous transformation of phase, the low phase noise, and other unique advantages, DDS is widely used in radar communications, electronic warfare and other military areas. The related core technology of current DDS chip was monopolized by foreign companies, so developing DDS chips with independent intellectual property rights will have broad market prospects and military applications.Based on the project of direct digital frequency synthesizer of a research institute, through in-depth study of design techniques of the abroad mainstream DDS.This paper proposes a DDS soft-core with CORDIC algorithm based on the structure of traditional direct digital frequency synthesizer for specific application. The frequency converted time of the designed DDS soft-core is 10ns, the bit-wide of frequency control word is 48, the bit-wide of phase control word is 14, the bit-wide of amplitude control word is 12, and the function of FM (frequency modulation), PM (phase modulation) and AM (amplitude modulation) can be implemented easily.after synthesising under SMIC 0.18um standard cell technology library, the synthesized results indicate that the DDS soft-core can operate in 100MHz, and the synthesized area is 1.34 mm×1.34mm,the gate-number is 0.11 million approximately.After introducing the current situation and development of DDS techniques, analyzing the working principle and architecture of DDS, as well as the CORDIC algorithm and it's several architectures for VLSI implementation.Then according to digital ASIC design flow, the phase accumulator,phase modulation adder,phase-to-amplitude converter and amplitude modulation multiplier in DDS soft-core are implemented with verilog hardware description language in register transfer level (RTL). The function simulation with modelsim and verification based on FPGA are completed. Finally, the gate-level netlist of DDS soft-core is synthesized by DC and the static timing analyzer of critical paths is finished.