.1024-point Complex Fft Processor For Asic Implementation

With the rapid development of electronic and integrate circuit technology, digital signal processing has been widely applied in various field, like radar, communication, imag processing, multimedia. Discrete fourier transform (DFT) plays an important part in digital signal processing as a basic calculation. Especially, Fast fourier transform (FFT) algorithm reduces the calculation quantity, which makes it much easier for implement and application. FFT is the core technique of digital signal processing, so there is strongly theoretical and practical significance in developing FFT algorithm and implement.The paper mainly discusses ASIC design of the FFT Processor. First, it elaborates the theoretical foundation of digital signal processing and principle of FFT. Then it compares the difference among the radix-2, radix-4, radix-8 algorithm and select the DIT radix-4 algorithm to design the FFT chip. At last, it ascertains the double SRAM common order architecture to implement the FFT processor based on area and performance.Considering the aspect of circuit design, it design a complex multiplier by CORDIC (coordinate rotation digital computer) algorithm, The CORDIC cell contains a constant constant-coefficient multiplier, which using the canonical signed-digit encoding and wallace tree adder to reduce the non-zero bits. The multiplier with a less critical path delay can increase the speed and reduce the complexity of the butterfly cell. In the FFT processor, the RAM address generator, ROM address generator and control logic are also designed.The design adopting the recommendatory design flows by synopsys finished algorithm verification, RTL coding, function simulation, logical synthesis, static timing analysis, auto placement and routing, layout physical verification, parasitic extraction, post-simulation using the most advanced design tools in IC field. The post-simulation shows the circuit achieves the request of high speed and high performance. The paper design a 1024-points complex data FFT processor based 0.18μm process. The chip with a layout size of 2.65×2.62mm~2 is fabricated by SIMC, it contains about 185 thousand logic gates. It finishs a 1024 points data FFT computation in the 5,127 clock period, that is 25.6μs with a clock frequency of 200MHz. The post-simulation shows that the total power of the chip is 384.5mW at the clock frequency. It shows a great advantage to the universal DSP and FPGA. The chip can output a FFT result with the SNR above 50dB by analyzing the post-simulation result using Matlab.