Studies On Direct Digital Frequency Synthesis Based On Modified CORDIC Algorithm

DDS is short for Direct Digital Frequency Synthesis. This is a new type of frequency synthesis technology which is developing qucikly in recent few years. This technique relies on the rapid development of integrated circuit technology and modern integrated circuit technology continues to progress as Moore's Law predicted. Direct Digital Synthesis is getting more and more attention under this environment. This frequency synthesis technology gains higher resolution?shorter conversion time?less noise than the traditional frequency synthesis technology. It is widely used in many of the electronic system.Phase accumlator, phase-to-amplitude converter, digital analog converter and low-pass filter form DDS. Tranditional DDS use a lookup table ROM or CORDIC algorithm to achieve phase-to-amplitude converter. Both methods have their advantages and CORDIC algorithm is widely used because its circuit is simple and storage capacity occupied by it is small. This paper presents a direct digital frequency synthesizer using a lookup table ROM and CORDIC algorithm both. Noise and the conversion time can be reduced and SFDR can be improved by this way. At the same time this method can reduce the number of iterations of calculation, thus reducing the consumption of resources hardware circuit. In this paper, the phase accumulator is 32 bits wide, and its output is 19, the high three bits used for selection the next seven is for ROM lookup table addressing and the low nine bits is for the CORDIC algorithm rotation calculations. SFDR are able to reach 113 d B as to RTL-level simulation, a relatively high spurious-free dynamic range. DDS This article has three operating modes: Ramp Mode, Profile mode and single-frequency mode.This article introduces many aspects of the direct digital synthesizer in detail, including its concept, development of home and abroad, its basic structural principle. Then the main point of this article is introdued, which is phaseamplitude converter's improvement. At last, the logic synthesis and back-end physical design was processed. The technology library employed is SMIC 0.18?m 1.8V 1P6 M standard CMOS technology library. The results of the compiling shows that DDS chip has 36,700 cells, of which there are 31,074 combinational logic cells, and 5626 sequential logic cells, with a total area of 6306063.06 ?m2 And the dynamic power is 1015.4m W, the static power consumption of only 465.65?W and the total power consumption is 1235.8m W..