ASIC Implementation Of Digital Down Converter Based On CORDIC Algorithm

With the development of 5G communication systems,the contradiction between the high-speed analog-to-digital converter(ADC)and the relatively low-speed digital signal processor(DSP)is further intensified,so that the digital down converter(DDC)is widely used in high-frequency communication In the system,it is used to reduce the speed,frequency and data volume of the output signal in the ADC.In order to develop a high-speed and high-precision DDC,this thesis designed two DDCs with different decimation modes based on the CORDIC algorithm and ASIC implementation in a 40 nm CMOS process,and embedded them into 4GS / s-12 bits ADC and In 3GS / s-12 bits ADC,realize SOC mixed design.The main research results are as follows:1.For the 4GS / s-12 bits ADC studied in this subject,a DDC with four down-conversion modes is designed.The decimation factors are 4,8,16,and 32,and the implementation of each mode is described in detail.The simulation results show that at the 4GHz sampling rate,the corresponding passband frequencies of 4,8,16,and 32 modes are 480 MHz,240 MHz,120 MHz,and 60 MHz,respectively,which meets the design requirements.Finally,based on the 40 nm CMOS process,the logic synthesis and digital back-end layout design are completed.The layout area of the digital part is 294 * 2570 square microns,and the total power consumption is 523 m W.The design is embedded in the 4GS / s-12 bits ADC to complete the final layout,and finally put into tape.The test results show that the DDC part can work normally.2.Based on the design of the four-decimation mode,in order to achieve more mode selection of the ADC design and expand the functional diversity of the ADC,a multi-mode DDC design scheme is proposed.The design mode is expanded from four modes to fourteen Mode and embed it in the 4GS / s-12 bits ADC and 3GS / s-12 bits DAC studied by the research group.The simulation results show that at a 4GHz sampling rate,the down conversion factors are 2,3,4,6,8,10,12,15,16,20,24,30,40,and 48,and the corresponding passbands are 956 MHz,615 MHz,480MHz,321 MHz,240MHz,197 MHz,162MHz,119 MHz,99.6MHz,72 MHz,69MHz,52 MHz and 38 MHz,the passband bandwidth is similar to the theoretical value,which meets the design requirements.The DDC studied in this subject provides a solution between high-speed high-precision ADC and relatively low-speed digital processing,and provides design samples for the realization of a new generation of communication systems.