Design And Implementation Of High-Speed And Low-Power SAR ADC

With the rapid development of science and technology nowadays, information that need handle become more and more. With higher reliability and need lower costs when compared with analog signal processing, digital signal processing has become the main-stream of the signal processing methods. Physical signals in the nature, such as sound, force, temperature, light, electricity, etc, however, are analog signals. So if you want to use digital signal processing method to deal with these analog signals, you need to con-vert these analog signals into digital forms first. So, the analog signal to digital signal conversion interface, analog-to-digital converter(ADC) appeared, and play a key role. There are many different kinds of ADCs, they have different advantages and applicable occasions. In the fields that have no requirement of particularly high speed and preci-sion, like wireless communication network and digital TV, successive approximation register(SAR) ADC is popular because of its small size and low power consumption characteristics. In recent years, with the rapid development of CMOS technology, chip integration becomes higher and higher, but the requirements of the supply voltage is becoming much lower at the same time, and the difficulty of analog integrated circuit design increases as well. At the same time, demand for low power consumption of chip, especially for mobile devices applications, becomes much higher as well.The main research goal of this paper is to design a ADC whose speed, accuracy and power consumption is good compromised. Based on the predecessors’works, we im-prove designed a 50-MS/s 10-bit asynchronous SAR ADC whose power consumption is only 180 μW. In order to speed up the ADC, we adopted the sub-range architecture, dividing the ADC into Coarse ADC(shorthand for CADC) and Fine ADC(shorthand for FADC) two parts. For high-resolution SAR ADC, delay of the feedback digital-to-analog converter(DAC), which mainly because of the long time that the large capacitors of the DAC’s MSBs needed to charge or discharge, becomes the main limiting factor of the ADC’s speed. For a Sub-range SAR ADC, circuits used to convert MSBs and LSBs can be designed relatively independent, which can avoid the DAC delay effect as in traditional structure on the overall speed. Unlike existing sub-range SAR ADC, the CADC and the FADC in our design are all realized with the SAR structure which have relatively lower power consumption compared with other ADC structures, with-out Flash structure. In order to enhance the speed and reduce power consumption, we integrated various technologies to implement the feedback digital-to-analog convert-er (DAC) of the FADC, including segmented capacitors array, monotonic switching method and insert redundant bits. For the CADC, we choose the multi-comparator SAR architecture, in which digital control logics are almost don’t needed, so that the CADC’s conversion speed is basically decided by the comparator delay and DAC delay, and the power consumption of the digital logic circuits can be greatly reduced.The proposed design was fabricated with TSMC 130-nm CMOS technology, and test result shows that it achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes only 186 μW at 50 MS/s with 1-V supply, resulting in a figure of merit (FoM) of 12 FJ/conversion-step. The core area is only 0.045 mm2.