Research And Design Of High Speed Analog-to-Digital Converter Chip

The increase in bandwidth of communication systems has placed tremendous demands on the performance of their building blocks.As a key building block in communication devices,analog-to-digital converter(ADC)chips,with the gradual spread of 5G networks in recent years,require higher speed,lower power consumption,and higher accuracy ADC chips.Therefore,researching on high-speed ADCs is a more attractive topic in both industry and academia.Due to the advancement of semiconductor process,the performance of device size and speed has been improved,the successive approximation type(SAR)ADC with the advantages of low power consumption,simple structure and small occupied area stands out to meet the design requirements of high-speed and low-power ADCs,and it is widely used and gradually becomes a current research hotspot.The main work of the thesis is to design a single channel 2bit/cycle SAR ADC with high speed and low power consumption for high-speed signal chain applications,to analyze the specific behavior of 2bit/cycle ADC,and to build a Matlab mathematical model to analyze the influence of non-ideal factors in ADC circuits.The ADC adopts the structure of "2bit/cycle+1bit redundancy+1bit/cycle",the first four conversions use three comparators to generate 2bit/cycle output compared to the traditional 1bit/cycle output with one comparator,which greatly improves the sampling rate.At the same time,the 1bit redundancy bit is added in the premise of high-speed conversion to provide sufficient redundancy range to guarantee the accuracy of the ADC;the last conversion of ADC uses only one comparator each time in the 1bit/cycle structure,Therefore,a recycling background self-calibration circuit is proposed to cycle the calibration of the other two idle comparators to track and calibrate the out-of-tune voltage c caused by the external environment.The proposed circuit can avoid the use of extra calibration phases and shorten the conversion time in real time;it can build a Verilog-A model with Gaussian distribution of capacitance values and analyze the effect of mismatch between capacitor arrays;it proposes a secondary folding compensation reference circuit to solve the problem of excessive temperature drift curvature caused by the first compensation and make the ADC work steadily in a wide temperature range.The ADC can operate stably in a wide temperature range.In this paper,an asynchronous 2bit/cycle SAR ADC is simulated and verified in the 40-nm CMOS process.The post layout simulation demonstrates that the ADC achieves the48.67 d B signal-to-noise distortion ratio(SNDR)and a 62.44 d B spurious free dynamic range(SFDR)at a 1.1v supply and a 250 MS/s input frequency.It consumes 3.1 m W at a sampling rate of 500 MS/s while achieving the effective number of bits(ENOB)at 7.79 bits and a figure of merit(FOM)of 28.01 f J/conversion-step.As a result,the performance index of this ADC meets the design requirements.