The Integrated Design Of Phase Locked Loop

The design of phase-locked loop is an important subject in modern integrated circuits. It has important effection in the field of radio frequency (RF) wireless communication and high speed wired communication, optical fiber communication and high performance digital circuits. The structure of the phase locked loop circuit can be found in any wireless receiving transmitter. From PLL published up to now, the technology has been applied in many fields, such as communication, radar, electronic countermeasure, remote control, radio and television. In addition, phase lock technology also has been widely used in some industrial fields, such as electric power, hydrogeology, production automation, mechanical processing and so on.The phase-locked loop is mainly composed of four modules, PD, LP, VCO and FD. It is a kind of automatic regulation system and can detect the phase difference of two signals. PLL is used in frequency synthesizer, clock recovery, clock generation and so on. In this design, phase detector was sampling phase detector, oscillator was ring oscillator composed of three stage inverting delay units, and the loop filter was passive second order low pass filter. This thesis used Cadence software to design each part of the circuit, completed pre simulation and layout design. Through design rule check, layout verse schematics and parasitic parameter extraction. After post simulation, the results of pre and post simulation were compared, then made corresponding improvement to circuit and obtain satisfactory results. Finally, completed the design of phase-locked loop circuit.In this paper, the PLL was designed in SMIC0.18μCMOS mixed signal process library to draw the schematic and layout of each module, and 1.8V supply voltage. Simulation results show that the power consumption of PLL is about 30mW, the output frequency of VCO is 0.8GHz-1.2GHz, at 1GHz the locked time is 12 μs.