Key-technologies Research And IC Design For Silicon Based Frequency Synthesizer In 60GHz Communication System

In recent years,60 GHz communication technology has become a hot research topic in the field of wireless communication,and this technology could be widely used in wireless personal area network,audio-visual signal transmission,wireless USB and other short-distance high-speed data transmission applications.At present,many major standardization organizations at home and abroad have proposed 60 GHz communication standards,such as ECMA-387,IEEE-802.15.3c,IEEE-802.11 aj,etc.,which specified the corresponding carrier frequency,channel bandwidth and other key parameters.Transceiver system and integrated circuit design based on the above standards are becoming research hotspots in related fields.As an important part of a transceiver system,the performance of frequency synthesizer directly affects the transmission data-rate and BER of the system.Therefore,the research and design of frequency synthesizer applied in 60 GHz communication system is of great theoretical significance and application value.The key technologies of frequency synthesizer applied in 60 GHz communication system using CMOS technology are studied in this paper.Based on research and analysis,the circuits of key modules in frequency synthesizer are designed,including voltage controlled oscillator(VCO),frequency divider,phase and frequency detector(PFD),charge pump(CP),phase-locked loop(PLL)and frequency doubler.The circuits have been taped out and measurement results are proposed.The structure and principle of phase-locked loop frequency synthesizer are discussed in this paper.The stability of PLL and the composition of phase noise of frequency synthesizer are analyzed.Based on the requirement of 60 GHz sliding IF transceiver system,the system-level topology of 48 GHz frequency synthesizer is proposed,and the behavior model of the frequency synthesizer is established.The phase noise of the frequency synthesizer is simulated based on the behavioral level model,and the loop bandwidth of the PLL is optimized according to the simulation results.Based on the optimization results of loop bandwidth,the time domain simulation of PLL is carried out to verify the lock-in function and determine the lock-in time of the loop.According to the calculation and simulation results above,the key parameter of each module of the frequency synthesizer are determined.The principle and typical structure of VCO are discussed in this paper.The generation and composition of phase noise are analyzed,and the optimization method of phase noise is studied.On this basis,a 24 GHz VCO circuit using complementary cross-coupling structure is designed,and the component parameters are calculated.The resonant components in the oscillator are analyzed and optimized.Switched capacitor arrays are used to expand the frequency tuning range and reduce phase noise.The VCO circuit has been taped out.The measurement results shows that,the output frequency of the oscillator ranges from 22.85 to 26.1 GHz,the phase noise at 1 MHz frequency offset is less than-95.56 dBc/Hz,the power consumption of the VCO core is about 6 mW.Principle and typical structure of frequency dividers are discussed in this paper.A 24 GHz high-speed divide-by-2 circuit and a 12 GHz pulse-swallow counter circuit are designed.The high-speed divide-by-2 is designed using pseudo-differential sourcecoupled logic structure.The circuits have been taped out.The measurement results shows that,with an input signal power of 0 dBm,the working frequency of the divideby-2 is 4~33 GHz,and the power consumption is about 3.6 mW,the working frequency of the pulse-swallow counter is 8~13 GHz,and the power consumption is about 7.7 mW.The principle and typical structure of PFD and CP are discussed in this paper.A 108 MHz high speed PFD and a CP circuit are designed.The PFD circuit is designed using edge-triggered structure.The CP circuit is designed using drain-switched structure with duplicated branch.The circuits have been taped out.The measurement results shows that,the phase detection range of the PFD is 355~ +355 degrees,and no obvious dead zone is found.The power consumption of the PFD is about 1mW.Charge pump circuit has good matching characteristics in the output voltage range of 0.25~1.05 V,and the mismatching error is less than 1%.The integration technology of PLL system,including module interconnection and isolation technology,is discussed in this paper.On this basis,a 24 GHz PLL chip is designed and integrated using circuit modules as VCO,divide-by-2,pulse-swallow counter,PFD,CP and loop filter.The chip has been taped out.The measurement results shows that,the frequency locking range of the PLL is about 23.3~25.9 GHz,and frequency step is 216 MHz,the phase noise at 1 MHz frequency offset is about-95.6~-98.3 dBc/Hz,the reference frequency spurious at 108 MHz is about-54.3~-62.5 dBc,the power consumption of the circuit is about 45.6 mW.The design and optimization of frequency doubler is discussed in this paper.Based on analyzation of the principle and typical structure of frequency doubler,a novel complementary push-push structure frequency doubler and a conversion gain enhancing technique using negative resistance are proposed.Compared with the classical push-push structure,the complementary push-push frequency doubler can generate differential output signals directly without additional Balun,which is convenient for system integration.Conversion gain enhancing technology using negative resistance could not only improve the conversion gain of frequency doubler,but also increase the maximum gain frequency.Based on the above technology,a 48 GHz frequency doubler is designed and taped out.The measurement results shows that,the output 3-dB bandwidth of the frequency doubler is 40~54 GHz,the peak conversion gain is-6.1 dB,the minimum fundamental rejection ratio is 29.5 dB,and the power consumption is 16 mW.