Research And Design Of The Key Modules Of Frequency Synthesizer

With the development of the Internet, Internet of Things(IOT) is gradually rising. Short range wireless communications and wireless control devices are extremely important. Therefore, the study of short-range wireless communication control system is more and more important.The RF receiver is a major part of a radio communication control system, its performance directly determines the application of wireless communication systems. As an important module, the performance of the frequency synthesizer receiver determines if the receiver can work properly. Therefore, this article focuses on the overview of the PLL frequency synthesizer, what more’s, the article designed key module of the frequency synthesizer for DRM receiver and superheterodyne receiver.Based on 0.18-um CMOS process, a phase frequency detector (PFD) and charge pump (CP) circuit for superheterodyne receivers is proposed. The phase frequency detector employs NSTSPC flip-folp and applies feedforward reset structure to achieve a low power consumption and a high speed which performance without phase dead zone. The charge pump circuit adopts a modified cascode structure in order to achieve a wide output voltage range and high current matching; moreover, an LC Voltage-Controlled Oscillator (VCO) and a loop divider circuit are proposed for the DRM receiver. The LC-VCO circuit uses a complementary cross-coupled topology, a PMOS tail current with filter, a high linearity C-V curve variable capacitor, which achieve a wide tuning range and good phase noise performance. The loop divider employs programmable PS-Counter structure, the division ratio is 7550～37162, can correct divide the input signal with frequency of 3G.The PFD and CP circuit has been taped out and messured, the measurement proved the reliability and good performance of the circuit, and meets the requirements of the superheterodyne receiver system. The LC-VCO and the loop divider have been layout and simulated, the post-simulation result showed the circuit meets the DRM receiver system specifications requirements...