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Research And Design Of PLL Using Ring Oscillator Applied To OFDM-UWB System

Posted on:2010-10-17Degree:MasterType:Thesis
Country:ChinaCandidate:J J DengFull Text:PDF
GTID:2178360275492277Subject:Microelectronics and Solid State Electronics
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Almost all modern communication systems need stable periodic signals,clocks, to provide basic timing for functions.The generation of stable periodic signal has been an urgent issue to be resolved due to the fabrication process limitation.This thesis has systematically researched the phase-locked-loop from the aspects of loop stability,loop noise performance and blocking circuit design.Also one low-cost high-performance PLL for MB(Multi-band)-OFDM(Orthogonal Frequency Division Multiplexing) UWB(Ultra Wide Band) transceiver have been designed where ring oscillator is chosen as the core circuit considering the factors like feasibility of integration,small area and multiple phases.First of all,a new 3-order close-loop linear model promised with the highest phase margin of the 3-order PLL loop is proposed,which updates the 2-order close-loop and 3-order open-loop models.Detailed reasoning procedure of input transient response for PLL 3-order linear model,along with its open-loop bode and close-loop locus root have been obtained to guide the loop stability design. Meanwhile,the optimum open loop bandwidth has been chosen to obtain the minimum integral phase noise in loop band.Then,in order to trade off between the cost and performance of super-fine phase when realizing the low-noise low-power high-performance PLL for UWB application,a optimum loop parameter design flow is tabled.Then,the thesis has summarized several noise models for oscillator from the side of applicability in form of noise source and ciruit respose mechanism.And in order to trade off between small gain and large frequency variation due to process and temperature fluctuation in high frequency application when realizing the low-jitter low-power high-performance VCO,two novel ring oscillators have been silicon-provided satisfying the requirernent,which have been implemented in 0.18-um standard CMOS process under 1.6 supply voltage.Finally,a reasoned analysis on charge pump and high-frequency divider was brought forward and directed the circuit desgin.Following the discussion on reference super and noise of CP,a high performance charge pump was shown.And the present divider can work under large frequency range with stable output amplitude.
Keywords/Search Tags:Ultral wide band, phase locked loop, integrate phase noise in band, ring oscillator, charge pump, divider, CMOS, frequency spur, phase noise optimization
PDF Full Text Request
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