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Research Of Multi Mode Chips Physical Design Methods

Posted on:2016-01-17Degree:MasterType:Thesis
Country:ChinaCandidate:X Y BaoFull Text:PDF
GTID:2308330482474952Subject:Computer architecture
Abstract/Summary:PDF Full Text Request
Recently, as intelligent devices are becoming more popular, the application of chip is increasing more and more. Multi mode chip design is one of the most important issues in modern IC design. Transition design methods, which are applied to multi mode chip design, face more and more challenges such as poor performance, high power consumption and large area. How to improve the transition design method according to the characteristics of the multi mode chip becomes the key to multi mode chip design.In this paper, we analyze three dimensions of multi mode chip design, such as clock tree optimization, pulse width scheduling, and hold time violation fixing. And new physical design methods of these aspects are proposed. The main contributions and innovative works in this dissertation are listed as follows:Firstly, a method of clock tree optimization considering on chip variation is proposed. This method decides which clock buffer can be replaced with adjusted clock buffer based on Monte Carlo analysis and clock structure to meet multi mode clock skew. Compared with previous method, the number of flip-flop which’s clock skew is out of range is reduced 19%, and the clock skew of chip is reduced 13%.Secondly, a method of pulse width scheduling considering multi mode timing constrain is proposed. This problem is solved based on the timing constraint, and it is optimized according to the pulse latch clustering and discrete pulse width. Compared with previous method, the time of adjusting pulse width is reduced 37.7%.Thirdly, a method to fix hold timing violation considering multi mode timing constrain is proposed. This method select buffer insertion point by heuristic algorithm, and select the buffer type by branch-bound algorithm. Compared with previous method, the area of inserted buffer is reduced 22%.
Keywords/Search Tags:multi mode chip, clock tree, clock skew, on chip variation, pulse latch, pulse width, hold time
PDF Full Text Request
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