Design And Implementation Of TSV’s Fault-tolerant Circuit In 3D-IC

3D-IC, due to it has overcome the bottlenecks which the two-dimensional integrated circuit met in nanoscale processes, is generally considered to be a continuation and transcendence of Moore’s Law, and has become one of the most promising technologies. Through Silicon Via(TSV), as its core technology, can significantly shorten the length of the interconnection line between the stacked layers chips, and effectively reduce the power consumption and improve chip performance. However, because the limitation of the manufacturing and packaging technology, TSV may exsist some dependability issues such as short-circuit failure or open-circuit failure, which will lead to the decline of 3D-IC yield and significant cost overhead. This paper mainly focuses on these dependability issues, and starts the associated fault-tolerant circuit design and implementation work of the Signal-TSV and the Clock-TSV, to ensure the high reliability of TSV.The main work and research findings in this paper including:1. Evaluating the failure probability of TSV in 3D-IC that owns different number of TSVs. In order to deepen the significance of this issue, based on those empirical data provided by HRI, IMEC,IBM, and other semiconductor vendors, the author utilise Matlab tool and the binomial distribution formula to conclude the failure probability of TSV in 3D-IC.2. Improving the Double-TSV and enhancing the circuit structure. To solve the reliability problems caused by Signal-TSV short-circuit failure, some relevant literature has suggested a Double-TSV to enhance fault-tolerant circuit structure. However, if TSV short-circuit happens, this circuit will appear the problem of large leakage power consumption. To solve this problem, we improve the circuit by cutting the leakage current paths. And the results of Hspice simulation show that the power dissipation of improved Double-TSV fault-tolerance circuit is reduced by at least 30.8%.3. In order to improve the repair rate of Signal-TSV fault-tolerant structure, the author has designed an extensible TSV chain single / double-fault circuit structure. Not only can it fix a single Signal-TSV failure in TSV chain, but also can repair two Signal-TSV failures simultaneously. The simulation results show that the circuit can work properly, and ensure the high reliability of the Signal-TSV in 3D-IC.4. To solve the clock skew problem of 2-TFU, the author proposes a compensation scheme of 3D clock skew, and has designed and implemented the circuit. In addition, the author also designs a 3D clock skew compensation circuit(3D CSCC) of high-precision, and the results of simulation show that the phase accuracy of this circuit can up to 6.86 ps, and its delay adjustment step can be controlled within the range of 1.4ps~4.2ps.5. Organizing the simulation analysis and experimental verification for 2-TFU structure that using 3D CSCC. In 40 nm CMOS process, the paper organizes this verification. The results show that the clock skew has gained 33.4% improvement, and compared with the 100μm TSV space setting in these literature, using this circuit, the TSV spacing in 2-TFU structure can be extended to 300μm. Thereby, the coverage of fault-tolerance TSV in chips improves significantly.