Study And Design Of Implantable High Energy Efficiency SAR ADC

With the development of microelectronic technology, implantable chips for biomedicalapplications become a hot topic. Analog-to-digital converter (ADC), as a core module ofimplantable system for recording bio-signal, need to be low power consumption and highenergy efficiency. The Figure of Merit (FOM) is used for measuring the energy efficiency ofADC. Currently, the FOM of high energy efficient ADC is less than100fJ/conv-step. Basedon chartered0.18μm CMOS, the design of fully differential100kHz10-bit SAR ADC wasstudied in this thesis.In order to improve the energy efficiency, the proposed ADC was designed from thefollowing aspects: low supply voltage, self-timing logic, split capacitive DAC and highefficiency of comparator.First, the supply voltage was lowered from1.8V to1V. Lowering the supply voltagewill lead to the bad non-linearity factor of input sample switches. Thus, a voltage doubler wasdesigned to double the voltage of control signals. Moreover, the input dynamic rang could beimproved. Secondly, due to the requirement of fast response in traditional SAR logic, theconsumption of comparator needs to be increased. However, with the proposed self-timinglogic, the comparator has more time to response, and less energy will be used. Thirdly,according to structure of improved split capacitive DAC, the proposed DAC was constructedas12-bit DAC to realize10-bit resolution. In comparison of10-bit split capacitive DACrealizing10-bit resolution, this can better overcome the error caused by the couplingcapacitance in the split capacitive DAC. Moreover, with using two unity capacitors in seriesas the most least bit capacitor, the12-bit split capacitive DAC settles the problem ofincreasing capacitor area. At last, the comparator is the key part of the proposed ADC. Theaspects of energy efficiency, precision and speed are the main considerations of thecomparator design. The comparator is composed of two stages. The first stage ispre-amplified circuit, and the second stage is latch comparator with high speed and low power.With the technology of output offset voltage elimination, the comparator could be of highprecision and high energy efficiency. By simulator Spectre based on Cadence, the proposed ADC was simulated. Simulationresults show that the ADC has better static performance. The maximum DNL is-0.4LSB/+0.4LSB, while the maximum INL is-0.3LSB/+0.6LSB. On the other hand, thesignal-noise-distortion ratio (SNDR) is61.3dB, the effective-number-of-bits (ENOB) is9.9,and the power consumption is7.0μW to achieve figure-of-merit (FOM)73fJ/conv-step. Theproposed ADC reaches the high energy efficient ADC level. The layout of the ADC wasfinished, and the area of core circuits is0.78×0.43mm2.