Research On Pipelined Successive Approximation Hybrid Structure Analog-to-Digital Converter Integrated Circuit

The high-speed and high-precision ADC plays an important role in the mobile communication system.The traditional high-speed and high-precision ADC is usually implemented by pipeline structure,but the traditional pipeline ADC has high power consumption and is not suitable for the battery powered low-power system.The pipelined SAR ADC has the advantages of high conversion rate,high resolution and low power consumption,which can better adapt to the performance requirements of the ADC in the current communication and consumer electronics fields.Therefore,the technical innovation and circuit design of the structure have gradually become the focus of ADC research.Based on TSMC-65 nm CMOS technology,an 8-bit 400MS/s successive approximation ADC with one step 1.5-bit/cycle is implemented.The ADC has 12.5% redundancy in the conversion period,and has a good fault tolerance ability for the comparator output error caused by capacitance mismatch,comparator offset and kickback noise.Compared with the traditional 1.5-bit/cycle capacitor switch timing,the new 1.5-bit/cycle capacitor switch timing proposed in this Chapter 3 does not need to set the preset bit,only needs two reference voltages,which not only reduces the design difficulty of the reference voltage bias circuit,but also increases the conversion speed and reduces the power loss.When the sampling frequency is 400MS/s at 1.2V power supply,the analog-to-digital converter realized in this Chapter 3 has SNDR of 40.88 d B,power consumption of 2.1m W,Walden Fo M of 58 f J/conversion-step and Schreier Fo M of 147.7d B at Nyquist input frequency.Based on TSMC-65 nm technology,a 12 bit 200MS/s two-stage pipeline successive approximation hybrid structure ADC is implemented.The ADC consists of two sub SAR ADCs and a dynamic residual gain amplifier.The first sub SAR ADC adopts the SAR ADC with 1.5-bit/cycle described in Chapter 3,and the resolution is designed as 6 bits.The second sub SAR ADC uses a SAR ADC of 1-bit/cycle,with a resolution of 7 bits.The dynamic residual gain amplifier is a dynamic amplifier with temperature compensation,which can stably provide the residual gain for the second stage sub SAR ADC to a certain extent,and the amplification factor is designed as 8.At 1.2V power supply,200MS/s sampling frequency and 27? TT process angle,the analog-to-digital converter realized in Chapter 4 has SNDR of 73.27 d B,power consumption of about 2m W and Walden Fo M value of 2.7f J/conversion-step at Nyquist input frequency.In this thesis,the key technologies of the pipelined SAR ADC are deeply studied.Through the innovation and optimization of the structure of the sub-level SAR ADC,the performance of the pipelined SAR ADC is improved.The applicability of the key technologies of the pipelined SAR ADC is verified through the analysis of the streamer and simulation,which will be used for the further study of the pipelined SAR ADC and other high-speed analogto-digital converter.