Theoretical Research And Circuit Design Of Ultralow Metastability High Speed Pipelined-SAR ADC

Analog-to-digtal converter(ADC)is an important mixed-signal circuit.It can convert various analog signals in the real world into digital signals,which facilitates the processing,transmission and storage of information.High-speed ADCs are widely used in wireless communication systems,image processing,and measurement tools.Among the various types of ADCs,the successive approximation register ADC is often used in low-power applications because of its high energy efficiency and low complexity,but its conversion speed is relatively slow.Pipeline-architecture ADC has higher speed and accuracy,but because of the larger number of stages,its energy efficiency is lower,and more interstage amplifiers are required,which also increases the design difficulty.Pipelined-successive-approximation-register ADC combines two structures of SAR ADC and Pipeline ADC to achieve a balance between accuracy,speed and power consumption.For high-speed Pipelined-SAR ADCs,the metastability of the comparator will increase the bit error rate(BER)of the conversion.Because of the higher sampling rate,it means that for each sample,there is very little time left for the comparator to determine.If the comparator fails to output a valid result within a given time,it will cause bit errors.In some instruments and serial link receivers,the bit error rate is required to be lower than10¹²,so even if the bit error frequency caused by metastability is not high and the signal-to-noise ratio(SNR)will not be reduced,but in some special needs,these errors are still problematic.This paper studies the metastability of high-speed Pipelined-SAR ADC from the aspects of theoretical derivation,modeling and simulation,and circuit construction.Perform theoretical analysis on the metastable state of SAR ADC and Pipeline ADC,analyze and model and simulate the asynchronous ADC.A structure based on two comparators is proposed to reduce the probability of Pipelined-SAR ADC entering the metastable state.Through modeling and simulation verification,this structure can reduce the probability of entering metastable state of the high-speed Pipelined-SAR ADC with resolution of 10-bit and sampling rate of 750MS/s to10¹².Based on modeling and simulation,this article carries out the design of the Pipelined-SAR ADC with resolution of 10-bit and a sampling rate of 750MS/s.Finally,in the 28nm process,when the power supply voltage is 0.9V,and the input signal frequency is close to the Nyquist frequency,at the tt process angle,the previous simulation results show that the sampling rate is750MS/s,and the ADC ENOB is 8.56.The spurious dynamic range(SFDR)is 64.15d B,SNDR is 53.27d B,power consumption is 5.771m W,and the Walden Fo M of 20.3f J/conv.-step.