Research On Key Technologies Of High-speed And High Energy-efficiency SAR ADC

With the rapid development of integrated circuit manufacturing process in the past decades,digital signal processing system based on integrated circuit,which has become more and more powerful and minimized,is widely deployed in 5g communication,Internet of things,industrial control and other fields,which need to interact with simulated signals in the real world.Analog to digital converter(ADC)used to convert analog input into discrete digital signal is an indispensable module of these systems.With the rapid development of information technology,such systems are developing towards higher and higher bandwidth to meet the increasing requirements of data stream transmission.For these high-speed communication system,high-speed and energy-efficient analog-todigital converter is a necessary module.Successive approximation register(SAR)ADC is a kind of ADC architecture that benefits most from the development of integrated circuit technology.The digitization characteristics of most of its key modules make it possible to achieve sampling rates of hundreds of MHz to GHz in mid-high precision(8 ? 10bit).For a general SAR ADC,its n-bit accuracy requires n quantization cycles,which is the key factor limiting the sampling rate of SAR ADC.Aiming at this characteristic,this thesis adopts the hybrid design architecture of SAR ADC and flash ADC.By embedding multiple thresholds required by flash method in the quantization process of SAR ADC,a 9-bit 2-bit/cycle SAR ADC per cycle is realized.Compared with the traditional multi bit SAR ADC per cycle,the capacitive load of sampling input is reduced to a certain extent since the CDAC of sampled signal is distinguished from the CDAC of threshold generation.The SAR LOGIC overhead for CDAC flipping is also reduced.This design adopts 28 nm process for simulation verification.The previous simulation results show that under 0.9V voltage,the ADC working at 900MS/s can realize 51.9d B SNDR and 63.9d B SFDR near the Nyquist input frequency,the effective bits are 8.33 bit,and the total power consumption of the circuit is 1.52 m W.