| In this thesis, design techniques for the phase-locked loop, phase detector and voltage controlled oscillator for clock and data recovery applications are studied.;A full-rate CMOS phase detector and the associated voltage controlled oscillator for Synchronous Optical Network (SONET) OC-192 systems were designed, implemented and tested. The two devices, implemented using a 0.18mum CMOS technology, consumed 14.9mW and 24.2mW respectively from a +/- 1.6 V power supply. The power consumption of the output drivers is not included in this calculation.;A new dual-substrate technique was used to overcome the small rail-to-rail supply voltage headroom problem that is characteristic of short channel length technology. The measurement and simulation results showed that the performances of the sample-and-hold phase detector (with 10-Gb/s NRZ data) and the 10-GHz complementary LC voltage controlled oscillator are superior compared to other reported designs employing existing technologies such as GaAs and SiGe.;The feasibility of substituting a digital CMOS process for those technologies traditionally used in high speed mixed-signal System-On-Chip (SOC) systems has been demonstrated. |
