Research And Design Of A 12bit 200 MS/S DAC With Digital Calibration Function

With the rapid development of information system,such as wireless communication and radar etc., high speed high precision DAC is increasingly important. And in the various types of DACs, current steering structure is a better choice to realize high speed high precision DAC. Deeply researched and analyzed high speed high precision current steering DAC architecture and key unit circuits, we have designed a 12-bit 200 MHz current steering DAC with calibration function based on the 55-nm CMOS process.In order to design a high speed DAC with speed of 200 MHz, we have analyzed the zero pole points distribution of current steering structure, and analyzed some non-ideal effects of the current steering DAC, including size and threshold voltage mismatchs beween transistors, layout voltage and temperature gradients. On this basis, combining with the 55-nm process characteristics, key unit modules performance indicators,we have determined the subsection points of 6+6 for 12-bit 200 MHz DAC.According to the current steering transistors mismatch error model, the larger the transistor size, the smaller the mismatch, but the larger area of the current steering part of the DAC, the greater temperature and voltage gradients, this causes larger INL error of the DAC. In this paper,we reduced the high 6-bit thermometer code current unit area, from 12 down to 4 precision accuracy, this greatly reduced the current steering part area, through the way of digital calibration, using a precision of 8-bit offset DAC to elimitate the mismatch of the current of main DAC, and improve its accuracy.Again, according to the current steering DAC performance indicators, basing on the 55-nm CMOS process, we have selected current steering transistors size, designed switch circuit and its drive circuit. As the need of digital calibration algorithm, designed the high accuracy high speed current comparator and digital calibration algorithm.Finally, basing on the 55-nm CMOS process, we have completed layout of key unit circuits and the integral current steering DAC, and finished post simulation of the whole 12-bit 200 MHz DAC. Post simulation result shows that under the sampling frequency of 200 MHz, SFDR achieved 72.1 dB, SNDR 69.6 dB. Power dissipation was 63 mW, the entire chip area was only 2.55 mm2.