Research And Design Of High Speed And High Precision Comparator

In modern society,analog-to-digital converters(ADCs)are widely used in communications systems,biomedical implants,and digitally assisted analog circuits.Among various ADCs,the SAR(Successive Approximation)ADC has many advantages such as remarkable digital features,simple structure and low power consumption.It is one of the hot spots of ADC research in recent years.The comparator is a key module of the SAR ADC.The speed,resolution,power consumption,etc.of the comparator directly affect the related performances of the SAR ADC.The pre-amplification regenerative latch comparator has the advantages of high speed,low power consumption and high resolution compared with other comparators,and is suitable for high-speed comparators.However,as the process size decreases,the device mismatch problem becomes more and more serious,which will increase the offset voltage at the input end and reduce the accuracy,which is not conducive to the application of the comparator in high precision applications.Therefore,this paper will focus on the design and implementation of comparators for high-speed,high-precision SAR ADCs.First of all,this paper briefly introduces the principle of comparators,analyzes the advantages and disadvantages of different structure comparators and the applicable fields.Secondly,for high-speed and high-precision SAR ADC,two different comparators are designed and related simulation analysis is carried out in this paper.Among them,the first one is a fast amplification comparator based on positive feedback,the second is a dynamic comparator based on voltage boosting technology.Based on the above two comparators,a new type of offset voltage correction circuit is proposed to reduce the offset voltage of the comparator due to transistor mismatch and capacitance mismatch,and improve the accuracy of the comparator.Finally,based on the research of the layout design method of the digital-analog hybrid circuit,the layout design and related post-simulation of the better performance comparator are completed.This design uses the TSMC 40 nm CMOS process.The pre-simulation results show that both comparators can work normally at 1.1V voltage and 500 MHz clock,and the dynamic comparator based on voltage boosting technology has better performance.The post-simulation and pre-simulation performances of the comparator are consistent with the variation of process angle and temperature.Both transmission delay and power consumption vary slightly with different process angle temperatures,and the performance is stable.The simulation results show that the maximum transmission delay of the high-speed and high-precision comparator is 120.5 ps,the maximum power consumption is18.72 ?W,the input offset voltage is less than 1/2 LSB,and the 200 ?V voltage can be distinguished.The comparator achieves 12 bit accuracy and meets the performance requirements of 12 bit 32MS/s SAR ADC for the comparator.