Phase Noise Research On Phase-locked Loop Based On Ring Oscillators

Phase locked loop(PLL) is able to produce clock signals that are in multiples of the reference input clock. These clock signals can be up to gigahertz range. Hence, it has been widely used for clock-and-data recovery in communication systems, clock generation in microprocessors, and frequency synthesis in wireless applications, etc.There are many specifications to gauge the performance of PLL but the most crucial specification is the phase noise. Factors affecting the phase noise are mainly thermal noise, flicker noise, shot noise, reference noise, substrate noise and power supply noise.Each of these factors is very different in nature from one another. Thus, it is very difficult to obtain a common method to quantify these effects to get the total phase noise relating to a PLL system. Conventional methods of calculating the phase noise are only useful for a rough guide because they could not take into account of all the effects mentioned. Some methods make use of sophisticated models to link the factors together to obtain the total phase noise but the result does not correspond well with that of the actual practical circuit. Other methods utilize graphical approach to calculate the phase noise from a spectral plot or the respective jitter from a time domain graph.Nevertheless, these methods could not quantify the phase noise accurately.In order to address the above problems, this thesis proposes a simple unified method to accurately calculate all the phase noise caused by the affecting factors and obtain the final total phase noise of an actual practical PLL circuit. The method uses a special superposition theory to unify all the phase noise transfer functions of the affecting factors in a practical PLL circuit. The unification of the transfer functions enables the total phase noise to be obtained by simple calculation and each of the transfer functions to be presented graphically. The calculation and the graphical representation can served as a very useful design guideline for the PLL integrated circuit designers to compare the effects of each factors and to design high performance PLL circuits.To verify the effectiveness of the derived formula, an output clock of 48 MHz charge-pump PLL is implemented using a standard 0.25μm CMOS technology. The simulation results show that a in-band phase noise of-88.6dBc/Hz and a out-of-band phase noise of-108.4dBc/Hz at 1MHz offset are achieved. These circuit simulationresults and the theoretical calculation results correlate very well with an absolute error of less than 2.54dBc/Hz.