Design Of A CMOS Charge Pump Phase Locked Loop

Phase locked loop is an important module of communication system. The entire performance of the communication system is greatly restricted by the performance of PLL. Based on 802.11.b, by phase noise model, principle of circuit design of PLL and other relative aspects, the main research of this theis are shown as below:Elaborated history and background of the PLL, and analyzed the principle and time domain phase model of charge pump PLL. The noise performance of the charge pump PLL and the loop parameters were discussed. The general structure, working principle and mathematical model of the voltage controlled oscillator were discussed. frequency divider, phase frequency detector, charge pump as well as a loop filter were discussed. Meanwhile some important mathematical formulas were deduced. Some problems of these modules designing had been presented. Described the principle and structure of sub-sampling PLL, and introduced the principle and mathematical model of sampling phase detector. Analyzed the noise performance and time domain phase model of the sub-sampling PLL. This thesis also discussed the problems and their solutions concerning over loarge capacitor area of sub sampling phase-locked loop’s LPF.Based on above research, this thesis proposed a design plan involved sub-sampling PLL, its core loop and FLL loop’s phase detector gain could be modulated by digital signal, and this feature made the anti-pvt ability of the PLL stronger, and the success rate of the PLL higher.The sub-sampling PLL’s circuit, layout and simulation were implemented in GSMC 0.18 μm process. Design of layout and simulation of performance have been done in this thesis. Based on the situation that GSMC 0.18 μm process does not provide inductance model, this thesis used ring oscillator as the oscillator of sampling PLL. To reduce tuning gain of voltage controlled oscillation, the voltage controlled oscillator with the tuning curves of all 8 segments was designed. Its tuning gain was 200MHz/V, and frequency range was 1.2GHz~2.8GHz. For the charge pump of FLL loop, current which could be adjusted in 5 μA~155 μA was used. And current regulation was controlled by the digital signal to reduce the effect of the variation of PVT.The simulation results show that the power consumption of the PLL is 8mW. The locked time of PLL is 12 μs at 2.4GHz. The phase noise of the VCO performance is-94.6dBc/Hz@1MHz.The phase noise of overall PLL is-108dBc/Hz@10KHz.