Research On Phase Locked Loop Based On Ethernet Physical Layer Chip

With the development of network communication technology,Ethernet technology has also developed vigorously,and has been widely used in local area networks,metropolitan area networks,wide area networks,and other aspects.From the 10 Mbps Ethernet technology of the 1980 s to today's fiber-optic Ethernet technology,in just a few decades,the development of Ethernet technology has been very rapid,all thanks to the advancement of Ethernet-related chip design technology and process levels.In order to adapt to the rapid development of Ethernet technology,new types of Ethernet physical layer chips are constantly emerging,and their performance requirements are becoming higher and higher.The phase-locked loop circuit is an important part of the Ethernet physical layer chip.A good phase-locked loop is very important for the entire Ethernet chip.The quality of its output clock determines the performance of the Ethernet chip to a large extent.Therefore,people Higher requirements have been imposed on the design of the phase-locked loop circuit of the Ethernet physical layer chip.However,with the continuous shrinking of CMOS technology and the needs of diversified markets,designing a high-performance phase-locked loop circuit has become a trend in the circuit design of Ethernet chips.And challenge.This paper focuses on the phase-locked loop circuit design based on the Ethernet physical layer chip.Aiming at the characteristic that the Ethernet physical layer chip circuit is easily interfered by internal noise when data is transmitted at high speed,a charge pump with low phase noise is designed.Phase-locked loop circuit.The charge pump phase-locked loop circuit designed in this paper mainly includes PFD,CP,LPF,VCO,DIV and other modules.During the design of this circuit,the in-circuit module was solved through in-depth research on the traditional charge pump phase-locked loop circuit.The dead zone of the PFD dead zone and CP mismatch encountered during the design.By analyzing and studying the stability conditions of the charge pump phase-locked loop circuit and the noise transfer mechanism of the charge pump phase-locked loop circuit and the method to reduce the noise,we finally designed A low-noise charge pump phase-locked loop circuit for an Ethernet physical layer transceiver chip.Among them,the VCO circuit of the phase-locked loop is a differential current deficient ring oscillator structure composed of three-stage inverters.The VCO circuit structure is not only simple,but also has the characteristics of low noise and good anti-noise performance.In an Ethernet chip circuit,the combination of the phase-locked loop and a circuit based on the PI structure can well realize clock recovery.This design starts with the working principle of the phase-locked loop,combines theory with experimental simulation,and uses the method of improving the structure of the phase-locked loop circuit and optimizing the parameters to achieve the purpose of reducing the output noise of the circuit.Compared with the phase-locked loop circuit in the traditional Ethernet chip,the phase-locked loop designed this time achieves lower phase noise output.Based on the SMIC 0.18?m CMOS process,the PLL circuit is simulated under the condition that the power supply voltage is 1.8V,the temperature is 27 ?,and the input reference clock frequency is 25 MHz square wave.When locked,the oscillator outputs a clock signal with a clock frequency of 250 MHz,the loop lock time is about2.06?s,the output phase noise is-110 d Bc / Hz @ 1MHz,its RMS jitter is 28.4ps,and the phase margin of the loop It is 55?.