Design Of Low Power Clock And Data Recovery Circuit Applied In SerDes Receiving System

High-speed serial communications are becoming increasingly important with the fast growing of human information in modern society. SerDes technique originally used in optical fiber communications is becoming mainstream high-speed serial communication because of its high speed, high capacity, low cost, strong anti-interference ability and other characteristics. A clock and data recovery(CDR) circuit is proposed in this paper by TSMC 0.18μm CMOS technology to provide clock signal and complete the recovery of data for 3.125Gb/s SerDes receiver.The CDR architecture is based on phase-locked loop(PLL) structure inputting 3.125Gb/s non return to zero(NRZ) data and outputting two-way 1.5625Gb/s NRZ data, an 1.5625GHz clock signal. In order to reduce system power consumption, the circuit’s power supply is 1.2V using a low-dropout linear regulator(LDO) to complete voltage conversion while improving CDR system’s power supply noise rejection. A full CMOS logic half-rate linear phase detector(PD) is adopted to reduce the frequency of voltage controlled oscillator(VCO), thereby reducing power consumption. VCO is based on three stages pseudo-differential string oscillator topology. The CDR circuit uses a charge pump(CP) to complete the transition from voltage to current. This paper uses a current steering technology to improve the speed of the CP, and an unity gain follower based on rail-to-rail structure to improve the range of output voltage.The entire CDR circuit occupies 0.321mmx0.534mm and the LDO occupies 0.3mm×0.375mm. In TT-corner of the post simulation with a 50 Ω load, the CDR circuit can operate successfully outputting 2 correct 1.5625Gb/s NRZ data and an 1.5625GHz cock signal. The peak-peak jitter is 0.0626UI for clok and 0.0497UI,0.0523UI for datas.The power consumption for CDR and LDO is 6.3mW with locking time 116.9ns. The LDO can provide precise power supply voltage for CDR circuit with the voltage temperature drift of 3.4ppm, power supply rejection(PSR) is-62.34dB whin frequency of 1kHz.