Research On Clock And Data Recovery Circuit For High Speed SerDes

With the continuous development of information technology,the data information is increasingly huge,people's request for information transmission rate become higher.In addition,with the continuous improvement of the global IC design level and the rapid development of CMOS manufacturing technology,the complexity,working frequency and data bits of the chip increase significantly.In view of the above reasons,the highspeed data transmission interface is crucial in the development of computer communication technology,and even becomes the bottleneck of the development of highspeed communication technology.In the high-speed data transmission between chips,due to the different delay of each signal path,the data synchronization of different signal paths is difficult when the clock frequency is several GHz.At the same time,due to the slow development of packaging technology,each chip pin is precious.Parallel communication is faced with great difficulties in high-speed data synchronization and chip pin packaging.Therefore,the communication mode of serial transmission is becoming more and more popular.As the interface of high-speed serial data transmission,the design and research of SerDes circuit becomes increasingly important.Due to the increasing demand of people,the Serdes circuit speed requirements are significantly improvred.The clock and data recovery circuit,as the key circuit of high-speed SerDes,its working speed and the ability of data clock recovery determine the performance of the whole SerDes.Therefore,the research of CDR circuit is crucial to improve the data transmission rate to reduce the restriction on chip performance and improve the user experience.In this paper,the CDR circuit is researched and designed,a variety of CDR architectures are analyzed,and a PS/PI CDR architecture suitable for high-speed SerDes is selected.The design principle of PLL as the core structure of CDR is systematically analyzed from three aspects: transmission function,locking accuracy and noise model.It mainly includes the second-order and second-class loop filter,the steady-state phase error and transient response related to the locking accuracy,and the noise transmission model of the phase-locked loop.Have a deep understanding of PLL system architecture and design principles.Based on the above theoretical analysis,CDR is designed based on40 nm CMOS process in this paper.The design content of CDR mainly includes the design of 12-phase clock VCO,PS/PI circuit,series circuit and frequency divider.The design feature of this paper is to use the inverter ring oscillator structure to realize the 12-phase clock.Compared with the traditional inverter single ring oscillator,the clock frequency is increased by 50%,and the orthogonal four-phase clock can be generated at the same time.Compared with LC oscillator,because there is no inductor and capacitor,the layout area is smaller and the manufacturing cost is lower.At the same time,because the frequency is greatly affected by the injection current,it has a large frequency modulation range;Compared with the differential ring oscillator,the inverter has no static power consumption,so it saves a lot of power consumption.Compared with the traditional 8-phase clock,the output is 12-phase clock,which has the characteristics of high interpolation linearity and high precision.In this paper,the sampling data is reduced to meet the working rate requirements of phase detector and digital filter.First 1:2 frequency division,and then 1:5 frequency division.The divided clock is used to control the deserializer to deserialize,so as to save the number of D flip flops in the deserializer,thus saving the layout area and power consumption.