Research And Realization Of 12-bit Pipelined ADC

With the rapid development of semiconductor technology, integrated circuit has stepped into a new era of SOC. High-speed, low-power A/D converters are widely used as analog IP, especially in SOC for communication and video processing. In this paper, a 12 bit 30MHz low-power pipelined A/D converter is designed using 0.35μm 3.3V CMOS mixed-mode process.Considering the tradeoff between high-speed and low-power, pipelined architecture is adopted. The whole ADC is comprised of 11 stages, 1.5 bit per-stage. In addition, dynamic comparator is adopted to eliminate most static power. Although such a comparator usually has a large offset, its effect on ADC can be eliminated by digital-error-correction. The design of operational-amplifier(OP) is the key to realize the pipelined ADC. The OP's constraints of gain and bandwidth can be deduced by analyzing the error of the ADC. Some improvement has been made in the design of OP to better balance the needs of high-gain, large swing and high bandwidth. All of the modules of the ADC are successfully simulated.In the end, the layout of the chip is designed in Chartered 0.35μm CMOS process, and the whole layout is realized by Full-custom.