Design Of Eight-phase VCO For High-Speed SerDes Application

Serdes is a kind of mainstram serial communication technolog. The technology of serial-parallel conventer can take full advantage of the channel capacity, thus greatly lows the cost of the communication and meets the need for the modern mass data exchange of I/O interface. In Serdes receiver, the clock and data recovery circuits(CDR) are used to receive and resample the high speed serial data by extracting the clock signal. Voltage controlled oscillator(VCO) is the key circuit module in CDR chip and the design of VCO is of great significance to the whole performance of CDR.Based on analyzing the basic principle of VCO circuit, the main task of the thesis is to design wide tuning-range multi-phase VCO which is applied in the quarter-rate CDR ciurcuit. Research background and status of VCO are summarized in the thesis. The principle and implementation method of voltage controlled oscillator are also discussed focusing on the the key technology of multi-phase VCO. The thesis applies the active inductor in the implementation of eight-phase VCO, which not only greatly reduces the chip area, but also realizes the wide-tuning characterization through the tenability of active inductor. The thesis describes the basic principle of voltage controlled oscillator and analyses the method about two kinds of oscillators based on energy compensation or negative resistance and the feedback theory. The cell of eight-phase VCO is based on the NMOS cross-coupled LC-VCO. A kind of varactors connections structure is used in oscillation network to improve the quality factor. In addition, the thesis summarizes two commonly used phase noise models:linear time-varying model and linear time-invariant model, laying the foundation for the phase noise optimization. The thesis also design the VCO output buffer circuit.The design is based on TSMC 0.18?m CMOS process and implements the design, historical simulation, layout design and post simulation of eight-phase VCO used in CDR.The whole chip area is 525?m×475?m. The post simulation results indicates the tuning range of this VCO is from 1.634GHz to 3.351 GHz. The phase difference of the adjacement clock output signal is about 45 degree and phase error is less than 0.4 degree.the phase noise is below -90dBc/Hz@1MHz in all frequency bands, system power consumption is lower than 24mW.