Research Of Physical Layer And Asic Implementation Of Key Modules For 100G Ethernet

Ethernet is widely used because of its low cost,high reliability,simple installation and maintenance.With the continuous development of Internet technology and the increasing number of users,the demand for data transmission and access bandwidth will become larger and larger.As early as 2010,the 40G/100G Ethernet standard IEEE 802.3ba was approved,and then in 2013,the new standard IEEE802.3bmTM/D1.1 was passed.At present,the IEEE802.3bs standard for 400G Ethernet will soon be promulgated.Therefore,the research on the physical layer implementation of high speed Ethernet has important theoretical and practical significance.First,this dissertation starts from two standards:IEEE,P802.3ba and IEEE802.3bmTM/D1.1 to introduce the 100GE physical layer architecture and the functional implementation of the physical coding sublayer(PCS)defined by them in briefly.Since the PCS clock circuit is based on the full digital phase-locked loop(ADPLL)structure,the ADPLL's basic concept,basic principle,common structure and main noise sources and the influence of noise sources on the jitter are introduced too.Then,the physical layer of 100G Ethernet is studied.According to IEEE802.3ba and IEEE802.3bmTM/D1.1 and design specifications,the system scheme of 100GE physical layer is determined,in which the electrical interface is 4x25Gbps.Based on the 0.18?m CMOS process using the semicustom design method to complete the 100GE transmitter PCS circuit design,including 64B/66B encoder,256-bit parallel scrambler,multi-channel distribution(MLD)circuit and 66:8 gearbox.In view of the high working frequency of PCS circuits,this dissertation optimizes the circuit structure and uses pipeline structure to design and come it true.Among them,for 64B/66B encoder,firstly,the encoding principle of 64B/66B encoder is analyzed in detail,and then the structure of optimized 64B/66B encoder is designed according to the coding principle,so as to ensure the speed of work to meet the requirements.In order to improve the scrambling speed,256-bit parallel scrambler is designed,and the structure of the parallel scrambler is optimized,so that it can improve the speed by means of pipeline mode.By the IEEE802.3ba standard,for 100GE,MLD must be distributed as 20 virtual channels,this dissertation skillfully puts the 4 input data into serial to parallel conversion,when at this time of parallel outputs,the output data is taken out by the way of(0,4,8,12,16),(1,5,9,13,17),(2,6,10,14,18),(3,7,11,15,19),so as to achieve the purpose of 20 virtual channels by the way of round robin distribution.For the 66:8 gearbox design,a round robin storage mode register structure based 66:8 gearbox is designed,so that it can start to output in a certain period of time,rather than only one time point by the special storage mode,so it can overcome the influence of input clock phase,greatly to improve the speed and stability of circuit.The test results show that the frequency of the gearbox can reach 700 MHz.In addition,in order to save area,a shared resource approach is adopted,which is to put the 20 counters on the outside of the gearboxes,only 3 counters are needed,saving 17,thus reducing the total area of the circuit.Finally,the PCS circuit is finished chip design using 0.18?m CMOS process,the chip area is 2.89mm2(including pads).The test results show that the circuit is correct and can realize the processing speed of 100Gb/s and the power consumption is 330.26mW.Finally,in order to provide multiple clock sources for the PCS circuit,the PCS clock circuit based on ADPLL is designed in this dissertation,which reference clock is 390.625MHz,and can produce 78.125MHz,644.53125MHz and 2.57GHz output clock frequency.The ADPLL uses a frequency and phase discrimination controller architecture with high resolution and wide locking range.Among them,the frequency divider based on semicustom circuit is realized by shift counting to improve the operation speed of the circuit.Full customized high-speed divider of 4 with two stage high speed divider of 2 is realized,this high-speed divider of 2 uses TSPC latch structure,in order to enhance the working speed.In addition,in order to speed up the phase locking,reduce the instantaneous phase locked differential,this dissertation adopts a forward prediction method.Finally,DCO uses three stage ring oscillator,the oscillator frequency is controlled by the coarse tune words(CTW)and the fine tune words(FTW),the CTW to control the output frequency fast approaching the target frequency and the FTW to control the final target frequency,in addition,in order to make the DCO work in a linear zone,a normal open oscillation circuit is designed.The PCS clock circuit is implemented using 0.18pm CMOS process,and it is taped out and verified,the chip area is 0.3416 mm2(including pad).The test results show that the maximum output clock frequency is 2.573GHZ and the corresponding peak-peak jitter is 27.64ps,the measured power consumption is 79.85mW.