Study And ASIC Implementation Of High-Resolution Sigma-Delta Modulator

The oversampling ΣΔ (sigma-Delta) analog to digital convertors (ADCs) are currently one of the most prevailing architectures for high-resolution ADCs. The fast development of integrated circuit’s manufacture process makes the thought of exchanging resolution with speed nicely implementable. ΣΔ ADCs have now widely applied to audio, digital TV, wireless communication and oil exploration. The fundamental structure of ΣΔ ADC was firstly proposed at the beginning of60s of last century, however, with the restriction of the manufacture process of integrated circuit, it was not paied much attention to. Until in later70s, with the fast improvement of the manufacture process, the idea of exchanging resolution with speed was gradually recognized. Many theory models and papers turned up in80s and ΣΔ ADC experienced a fast developing period. Principly speaking, as the order of analog modulator in ΣΔ ADC increases, the noise performance of ΣΔ ADC would be better and the structure stability would be worse. Normally, the stability characteristic is confirmed by post-simulation of modulator circuit and there is no theory system that could direct to design a high-order stability-free ΣΔ ADC. How to design a high-resolution, high-stability ΣΔ ADC is still a research hot spot and a diffcult issue.ΣΔ ADC is divided into two parts structurely:a front-end analog modulator and a back-end digital filter. Digital filter, whether from structure or from implementation, is mature, and as it only covers ditigal circuit process, it is relatively simple compared with analog modulator. The digital filter in ΣΔ ADC is usually comprised of two stages:the first stage mainly functions as a decimator to reduce the sampling rate. Comb filter is a prevailing structure in this stage, which is usually implemented by cascaded carry chains. The second stage is normally a FIR filter, which functions mainly as an anti-aliasing filter and at the same time also a decimator against the first stage. The performance of front-end analog modulator plays a decisive influence on the whole ΣΔ ADCs, so most of the researchs on ΣΔ ADCs mainly concentrate on the front-end analog modulator. In essence, the analog modulator is also a filter, which prepells the noise of base-band to high-frequence area. These high-frequency noises will eventually be removed by back-end digital filters to achieve high-resolution then. As said above, the higher order of analog modulator, the better will be the performance, however, the worse stability of modulator. Currently, single-loop fourth-order modulator is used often. One-order and two-order modulator is unconditionally stable, thus a structure named MASH is created, which constitutes several one-order or two-order single-loops. However, MASH structure proposes a high standard for circuit matching, which under current manufacture process, is hard to achieve. Single-loop modulators are still a mainstream of researches nowadays. This dissertation thus concentrates on studies of high-order modulators and mainly includes the following issues, firstly, analyzing the stability of high-order modulators using root locus plot. With this plot, the stable signal input range will be given as long as the noise transfer function (NTF) is provided. Secondly, based on the previous researchs, the dissertation advances a standard method of designing high-order analog modulators. Based on this method, the NTF can be quickly calculated according to the required noise performance. Thirdly, a comparative analysis is made on currently prevailing modulator structures and with a concrete example; the design process is given on how to choose modulator structure based on the calculated NTF. Fourthly, based on the chosen modulator structure, the concrete ASIC circuit implementation of a single-loop fourth-order analog modulator is provided.The structure of this dissertation is as follows:The first chapter is the introduction of the dissertation. In this chapter, the research background is firstly given. After that, it introduces the development roadmap of EA ADCs. Then, it presents the content and the purpose of this dissertation.The second chapter concentrates on the structure of ΣΔ modulators. It firstly proposes a structure model for ΣΔ modulators, and based on it, it then gives a deep analysis on the stability of the structures using root locus plot. At last, an introduction to the MASH structure is also presented.The third chapter designs a single-loop fourth-order EA modulator based on the methods presented in chapter2. Non-idealities of the designed ΣΔ modulator are analyzed and simulated using Matlab.The fourth chapter discusses the circuit implementation of the designed ΣΔ modulator. The pre-simulation results are given for each sub-module and the whole modulator.The fifth chapter describes the layout design of each sub-module in the modulator, and simulation results are also presented. At last, the whole modulator is simulated after evaluating the parasitic parameters. Non-idealities such as voltage variation are also simulated. The simulated resultes verify that the implemented modulator is functional and achieves the required SNR.The sixth chapter gives the test scheme and test bench for the modulator chip. Test results are obtained.The seventh chapter summarizes the main ideas and the innovations of this dissertation, and then points out the direction of future work.