The ASIC Design Of Frequency Synthesizer Used In SoC

Based on the general requirements of the readers , two ASIC designs of frequency synthesizer were implemented with SMIC 0.18μm CMOS technology library in this paper. One is a direct digital synthesizer based on ROM structure ; the other is an all-digital phase-locked loop.In the DDS chip designing ,based on the analysis of specific application requirements of DDS, the paper defined the main performance parameters and system structure, and designed the sub-module circuits . The accumulator module combined the carry line and pipelined architecture together to improve the frequency and reduce the resource utilization; the compression algorithm in ROM module is based on the 1/4 symmetry of sine function and Hutchison algorithm, which made the compression ratio as high as 49 times . What’s more , the power consumption and die area had been greatly reduced . The back-end physical design and simulation had been finished in SMIC’s 0.18μm CMOS process. The finished area of the DDS layout is 260×260μm~2, and the equivalent gate count is 1021. The average power consumption is 7.79mw. The frequency resolution is 0.058Hz ; when the output frequency is 14.65MHz, the stray is more than 70dB. The highest operation frequency of DDS is up to 100MHz .In the ADPLL chip designing, the ADPLL had a ring digital-controlled oscillator composed by enabled units, with the ring structure divided into two parts in terms of the coarse tuning part and the fine tuning part. It included the characteristic of wide locking range, high locking resolution, and low power consumption. What’s more, the locking range can be further expended according to the demand. Different from the traditional design, this design was based on CMOS standard cells and used synthesizable Verilog HDL for sub-modules description, so it could be easily implanted to different processes, and both the design time and complexity could be reduced. This ADPLL can operate from 72.95MHz to 353.66 MHz, the resolution is 2.47 ps , the locking time is smaller than 35 cycles. When the output frequency is 300MHz ,the peak-to-peak jitter is 168ps and RMS jitter is 38.42ps. With a 1.8V power supply, the proposed DCO has a power consumption range from 0.7mw to 1.52mw. The finished area of the ADPLL layout is 274μm×274μm, and the equivalent gate count is 4006.