Research On Delay-Locked Loop Based TDC ASIC In 180 Nm CMOS

High-precision time measurement is one of the main tasks of readout electronics in nuclear and particle physics experiments,and it also plays a crucial role in fields like medical checking,fluorescence lifetime imaging or autonomous vehicle research and so on.So far,a variety of precision time measurement implementation schemes have been proposed,and the most popular one is based on the discrimination and time-to-digital conversion.Time-to-digital converter(TDC),as the key component of such technique,dominates the final time measurement performance,and TDCs with hundred-piscosecond precision have a wide range of application requirements.At present,most time measurement electronics systems in domestic applications are designed with imported TDC application specific integrated circuits(ASICs)or field programmable gate arrays(FPGAs).For instance,the HPTDC ASIC designed by the CERN microelectronics group is employed in the time digital electronics of the Multi-Wire Drift Chamber in the Lanzhou Heavy Ion Research Facility external target experiment,and it obtains 100 ps bin size.In the WCDA front-end electronics of LHAASO project,FPGA based TDC is utilized to achieve the resolution better than 300 ps RMS.Compared with ASIC,FPGA is more flexible,reconfigurable,and has shorter development cycle.However,because FPGA is a general-purpose device,it is impossible to achieve specialized design under the best resource optimization goal while implementing TDC design.Additionally,it suffers from high cost and high power consumption when applied in large scale.The ASIC TDC has obvious advantages in these aspects because of the customized design,which greatly improves resource utilization,reduces circuit power consumption,improves system integration and reduces average cost.This work focuses on the design of a customized TDC ASIC and aims to make technical preparations for similar applications in the future.A Delay-Locked Loop based TDC prototype ASIC was designed and fabricated in 180 nm CMOS technology,and then a testing platform was set up composed of designed ASIC evaluation module,FPGA board and other parts.The performance of the TDC prototype ASIC was evaluated with such testing platform at last.This paper is organized as follows.The first chapter introduces the research background of this work.Some typical applications with hundred-picosecond precison TDCs are introduced,including fields of nuclear and particle physics experiments,biomedicine and autonomous vehicle and so on.The performance requirements of the TDC prototype ASIC are listed in the end.Chapter 2 presents the basic concepts of TDC.The advantages and disadvantages of FPGA based TDC and ASIC TDC are discussed at first,then the basic principles and implementation methods of commonly used TDC ASICs are introduced in detail.At last it describes the performance metrics that often apply to TDCs while designing.Chapter 3 introduces the design scheme and overall architecture of the prototype TDC ASIC,and as well details of all the main circuit blocks.In Chapter 4 the evaluation of TDC prototype ASIC performance is presented.The methods of TDC evaluation are introduced and set up of testing platform is shown.Tests have been conducted and the results are presented at last.The results show that the chip achieves a 160-ps bin size with time resolution better than 60 ps RMS,and a 20?s dynamic range is achieved.The differential nonlinearity(DNL)and integral nonlinearity(INL)are better than 20.3 ps and 23.4 ps,perspectively.The last chapter summaries this dissertation and outlines the future research work.