Design And Performance Analysis Of SHA Algorithms Based On ASIC

SHA?Secure Hash Algorithm?is a set of cryptography hash functions designed by the United States National Security Agency?NSA?.Basing on its advantages:for different input messages,it has very high probability to get different digests,SHA is widely used in cryptography,data integrity detection and other fields.However,because SHA algorithm needs many iterations to get the final digest,it has large amount of computation.directing to very long messages,it is important to complete the calculation as soon as possible.Then,how to implement high throughput SHA algorithm based on ASIC is becoming a big problem.The topic originates from the development project of Micron Company,aiming to design a SHA algorithm module with high throughput and small area.Therefore,the following research work have been carried out in this paper:1.To solve the problem of large amount of computation in SHA-2 algorithm,W-value prediction method is used,the calculation of W₁₆6 is starting when W₀ is transmitted.Under the condition of accurate calculation,the number of 64 bits additions per cycle is reduced at least once,in this way,SHA-2 module is easier to meet the timing requirements.2.Based on deep studying the generating mechanism of pseudo-random number in SHA-3algorithm,the pseudo-random number generator in the?step of SHA-3 algorithm is replaced by the calculated value,which solves the problem of large circuit area of pseudo-random number generator in SHA-3 algorithm.Under the condition of meeting the timing requirements and accurate calculation,SHA-3 module saves the area of an 8-bit LFSR.3.By using parallel operation and loop multiplexing technology,a general algorithm architecture suitable for both SHA-2 and SHA-3 is achieved.This architecture has the advantages of high module utilization and small area.At the same time,by controlling the valid bits of input data,the architecture can be applied to data of any input scales.Synthesis results show that under the conditions of SHA-2 and SHA-3 algorithm modules contain six sub-algorithms,meanwhile,the time sequence meets the requirements,the area of the module is optimized firstly.Then I finally get the result that area of SHA-2 module is63312?m2,and the area of SHA-3 module is 32421?m2,respectively.Simulation results show that the SHA algorithm implement by ASIC in this paper is consistent with the algorithm implemented by software,which proves the correctness of the algorithm module design in this paper.In terms of throughput,for data over 30000 bits,the throughput of SHA-2 algorithm module is above 20 Gbits/s when running SHA-256algorithm,above 32 Gbits/s when running SHA-512 algorithm,respectively.For data over30000 bits,the throughput of SHA-3 algorithm module keeps above 23 Gbits/s when running the SHA-512 algorithm,and 32 Gbits/s for other SHA-3 algorithms.The research works based on SHA-2 and SHA-3 methods improving and circuit realization provide a foundation for standardization of DMA module in the company's project development,it also provides technical reference for system development that needs data consistency detection.