The Design And Verification Of 12bit 60Msps Pipelined ADC

Recently, we have entered Post-Moore period. However, with the development of integrated circuit processing technique, the level of circuit integration is improved significantly, which greatly promotes the development of IC design technology. As the bridge of connecting the simulate World and DSP, ADC has become an essential part transforming analog signals into digital signals. But the performance of ADC is a bottleneck of the whole system. This thesis aims to design pipeline ADC circuit used in FHD video image sensor which can scan line by line.Firstly, this thesis analyzes the basic principle of ADC, makes a basic introduction and comparison about some common types of ADC. Then specific design of pipeline ADC circuit is conducted. According to performance requirements of the system, Index calculation is made, including confirming capacitance size of all levels, the gain and GBW of opamp, calculating bandwidth and verifying with simulink model. In order to realize accurate quantization of signals and maintaining the circuit, continuously-changed analog signals are sampled with circle time interval; gain-boost opamp is designed to improve linearity of signal establishment; pipeline structure with 1.5 precision of each level is applied for realizing redundancy encoding and decreasing impact of comparator's unbalanced voltage on precision; a new type of pre-amper comparator structure to eliminate static power is put forward meanwhile. By comparing traditional latch-up comparator with multi-level comparator, performance advantage of this kind of comparator is presented. Afterwards, elaboration of design proposal and key point of Pipeline ADC is made. The chip of this Pipeline ADC is designed with HUALI 55 nm CMOS technique. Analyzed simulation results with FFT, dynamic parameter is gained as follows: SFDR: 88.57dB; SNR: 72.51 dB; SNDR: 72.3dB; ENOB: 11.72 bits.After the Pipelined ADC chip taped out, designing the test plan and testing it. Analyzing the basic principle of the test, at the same time, finish the ADC evaluation board design and build test platform. Finally, the Test results show that In the range for full swing, When the input sine signal frequency is about 1 M, use crystal oscillator of 60 M as the sampling clock, Based on the result of the logic analyzer to FFT analysis dynamic parameter is gained as follows: SFDR: 66.9dB; SNR:65.5 dB; SNDR: 62.8dB; ENOB: 10.15 bits.