The Research And Design On The Key Circuits Of Pipelined-SAR ADC Based On 65nm CMOS Process

With the rapid breakthrough of related technical field in videos,wireless communications,images and so on,The development and population of the portable electronic devices,the design of ADC possessing high-speed,high-resolution and low-power consumption have became a great challenge.Pipelined-SAR ADC has aroused a widespread attention because of combining the advantages between Pipelined ADC and SAR ADC,which achieved good balance among speed,resolution and power consumption.The thesis mainly seeks to study and design sampling switch and residual amplifier based on 65nm CMOS process,which fits the 10bit 80MS/s two-stage Pipelined-SAR ADC.The main work of this paper are as follows:(1)A high-linearity bootstrapped switch is designed.The Coupling Effect of Cut-off Switch is reduced to weakened the impact on SAR ADC conversion by adding a dummy switch to the bootstrapped switch.In addition,a coupling capacitor is added to the gate of the bootstrapped switch so that the clock feed-through effect of single-ended can simultaneously act on both the positive and negative sampling capacitances,and the voltage error generated by the clock feedthrough is eliminated by the differential structure.The post-simulation results show that it achieves a SFDR of 112.7dB at the sampling rate of 80MHz under the condition of 1V supply voltage and 1Vpp input signal,which meets the system requirements of 10bit 80MS/s two-stage Pipelined-SAR ADC.In addition,it achieves a SFDR of 105.1 dB,92.26dB,58.6dB(worst case)respectively at the sampling rate of 200MHz,500MHz,800MHz.(2)A telescopic amplifier with high-speed,low-powers consumption is designed as residual amplifier.lt is designed by employing gain 'boosting technique and subthreshold technology.The post simulation result shows that the DC gain of Amplifier is 72.9dB,the unit gain bandwidth is 1.10GHz,the phase margin is 86.7°at 1V supply,meanwhile,these above indicators can also satisfy the design request under different temperatures and corners.When we apply amplifier to relative MDAC,we measure that the settling time is 5.Ons,which meet the system requirements of 10bit 80MS/s two-stage Pipelined-SAR ADC.The overall power consumption is about 1.3 1mW and it achieves a FoM of 630MHz·pF/mW.