Researches And Designs Of Digital Calibration Algorithm For Pipeline ADC Based On LMS

With the rapid development of integrated circuit industry and CMOS semiconductor manufacturing process,digital signal processing has made significant strides and has become an important discipline.Digital signal has been applied to many scenes because of its high anti-interference ability and good confidentiality.Analog-to-Digital Converters(ADCs)play a role as a bridge between the analog world and the digital world,and its main function is to convert analog signals in nature into digital signals,which can be processed in digital system.With the high conversion speed,high resolution and low power consumption,pipeline ADCs are widely used in digital image processing,wireless mobile terminals and digital signal processing systems and other fields.Various non-ideal factors have a great influence on the performance of the pipeline ADCs,such as capacitive mismatch,op amp limited gain and other factors.At present,digital-analog converter with digital calibration technology has become a research hotspot in recent years.For the nonlinear errors of pipeline ADCs,this paper mainly analyzes the basic structure of pipeline ADCs and the impact caused by capacitance mismatch and other nonlinear factors of pipeline ADCs.Then make error model of nonlinear errors in pipelined ADCs.For this error model,this thesis introduces a digital background calibration algorithm based on LMS,which constructs two calibration loops to iterate first-and third-order error coefficients of the nonlinear error respectively.This algorithm uses high-speed high-precision reference ADC to replace traditional low-speed,high-precision references ADC.The calibration technology can reduce the influence of capacitive mismatch,op amp limited gain and other nonlinear factors,and improve linearity of the system effectively.16 bit pipelined ADC and entire digital calibration system were modeled with Matlab/Simulink.The simulation results showed that the ENOB,SNDR,and SFDR of the pipeline ADC with sampling rate of 100MHz and input rate of 45MHz were improved from 9.6 bit to 15.7 bit,59.5dB to 96.6 dB and 64.9dB to 110.9dB respectively after calibration.Then verified this calibration algorithm using Altera's Cyclone IV development board,ENOB,SNDR,and SFDR were improved from 9.6 bit to 12.7 bit,59.5dB to 78.6 dB and 64.9dB to 83.8dB respectively.