The Digital Background Calibration Algorithm For Multi-Channel Time-Interleaved Analog-to-Digital Converter

Digital Signal Processing (DSP) technology nowadays is employed in more and more areas like broadband wireless communication (BWC), biomedical sciences and computing and instrument controlling. As the technology of DSP and the critical device of the communication physical layer, the high performance Analog-to-digital converter (ADC) usually used in mixed analog-digital integrated circuit is becoming more and more important. To some certain extent, the bandwidth, speed, accuracy, hardware cost, power consumption and reliability of an ADC determine the performance and functionality of the wireless base stations and terminals.Parallelization is an effective method to break the constraints on the sampling rate as the structure of a single ADC has reached the limit of the condition of design and process. A typical time-interleaved ADC has several paralleled channel ADCs (Sub-ADC), which sample the input by turns. The applying of this parallel structure can increase the overall sampling rate of the entire ADC while maintain high precision.However, when it comes to actual cases, there are several non-ideality factors between channels of the time-interleaved ADC, such as offset mismatch, gain error and sample-time error, which greatly reduce the resolution of the time-interleaved ADC. To enhance the performance of time-interleaved ADC, we need to eliminate these mismatches through calibration.This paper presents a new correlation-based digital background sample-time error calibration method and a new sampling switch applied to this specific calibration method. It can be employed in most situations, and it significantly expands the input signal conditions to wide-sense stationary signal which is common in communication systems. It can also be applied to any number of channels of time-interleaved ADC, which is the essence of time interleaving. The new calibration circuit is simple enough to be applied to other similar circuit and systems, and it has small hardware cost and low power consumption in addition.The experiment of the digital background calibration method proposed in this paper is based on a 2-channel 14-bit 200-MSps time-interleaved ADC prototype chip and a Xilinx Virtex-4 FPGA board. The experiment results show that the calibration method completely eliminates the constraints of the sample-time error on the overall performance of the ADC. Based on what I observed, the spurious-free dynamic range (SFDR) increases 30dB after calibration, the signal-to-noise-and-distortion ratio (SNDR) 15dB and the effective-number-of-bits (ENOB) 2-3-bit.