Research And Design Of The Digital Control Circuit Based On RapidIO2.1Physical Layer IP Core

With the rapid development of the embedded processing technology, the embedded system with high performance interconnection will face enormous challenges. RapidIO interconnection architecture is currently the world’s first and only international standard for Embedded Systems Interconnect (ISO/IEC18372), can meet the application and basic demand of embedded equipment. From superiority the RapidIO shows and the gap between domestic and foreign development situation, we can see that domestic RapidIO interconnect technology both in the aspect of application and research are at the initial stage. Therefore, try to develop RapidIO IP core is particularly important.RapidIO interconnection technology is based on packet switch and full duplex communication mechanism of point to point between devices, which can solve the bottleneck of bus technology brings. RapidIO2.1is the latest Internet protocol architecture, serial protocol is divided into logical layer, transport layer and physical layer. Through careful analysis of the physical layer, the digital control circuit of physical layer is divided into the flow control layer, serial protocol layer and physical coding layer, the working principle and design ideas are elaborated. Verilog language is used to design the modeling and register transfer level circuit. In order to make the physical layer IP core testability, built in self test circuit is designed for meeting this requirement. Improvement of assembly line method8b/10b codec compared to traditional look-up table method, area and power consumption are greatly improved. The binary automatic frequency correction algorithm for5GHz phase locked loop (PLL) is proposed. It greatly shorten the lock time, the simulation results is22.5s. These improvement of circuit structure can help enhance the performance of physical IP core system.The digital control circuit of physical IP core are abundantly verified step by step from the module level, hierarchy level and system level. The result shows that digital control circuit can complete error recovery and flow control function. Serial RapidIO2.1physical layer IP core is taped out in HUALI40nm CMOS technology. By testing on the FPGA hardware platform, BER of physical layer1P core is less than10-13in5Gbps serial rate. Verification and test results shows that function and characteristic parameters of the physical layer1P core meet the basic requirements of serial RapidIO2.1protocol.