The Design Of 8 Bits RISC-CPU

The design is based on a project of cooperating with an IC design cooperation. The purpose of the project is to build the course for the fresh IC design engineers. The project focuses on a RISC-CPU and develops an IC design flow.RISC is the acronym of Reduced Instruction Set Computer. Compared with the common CPU, RISC not only simplifies the instruction set but also makes the computer construction simpler and more reasonable. Consequently it increases the work frequency.This paper discusses the construction of RSIC-CPU and introduces how to design a RISC-CPU. Then the paper focuses on an 8 bits RSIC-CPU. Combined with multi-EDA tools——NC-Verilog simulation tool from Cadence, Design Compiler synthesis tool from synopsys, SOC Encounter placement and routing tool from Cadence and Calibre layout verification tool from Mentor, it comprehensively and systematacially introduces the flow and methodology of RISC-CPU design which is from module partition, design import, function simulation, logic synthesis, timing simulation, placement and routing to layout verification. Meanwhile, low power design and pipeline design are set forth to satisfy the design's requirements.