Timing Verification Of X Microprocessor

As the design size keeps growing and the feature size keeps scaling down in integrated circuits, the effects of short channel and interconnector are major factors in determining the performance, so that timing convergence has become one of the most intractable problem for designers. Timing verification is to analyze the timing characters of a circuit, and to check whether or not it could satisfy our requirement in performance. Timing verification plays a very important role in the work of verifications, it is the main way to help designers finding bottlenecks in their circuit.Based on the study of timing verification presently used in the word and the analysis of their advantages and disadvantages, including dynamic simulation, static timing analysis and statistical timing analysis, we analyzed them comprehensively, and compare the difference among them in diffenent design hierarchies. Furthermore, we studied the main approachs to characterize the timing model of a circuit, and applied them in the timing verification of X microprocessor in a flexible way.X microprocessor is a full-custom circuit designed under 0.18um process, it contains a lot of complicated design types. To improve its performance, we used more than 7000 cells in layout implemetation, including some custom modules such as Cache and ROM of microcode. So it is a great challege for us to create timing models and complete timing verification. According to the requirements above, we apposed a way of hierarchical analysis. The whole processing of timing verification contains a gate-level static timing analysis and a logic simulation with accurate delay information. On the basis of creating timing models of basic cell, we brought forward the method of characterize blocks in the design, which takes the idea of mode dependecy. By LVS in transistor-level, cell-level and blackbox-level respectively, we can ensure that the cells and instances in the logic netlist would be consistent with those in the layout netlist. We accomplished the full-chip static timing analysis of X microprocessor, and made a detailed analysis such as critical-path checking in the circuit. After describing the delay specifications of all cells in their function modules, we can accomplish the work of delay back-annotating which provides actual delay information in the design for an accurate logic simulation, and have a more strict verification on the function and performance of the microprocessor.In the thesis, we implemented a cell-based timing analysis of a full-custom design, which shows the idea of hierarchical analysis.