Study On Addressable Yield Analysis Chip’s Verification Flow

With the decreasing of critical dimension, the influence of chip defects on yield is more and more serious. Yield analysis chip is a proper tool to analyze the process of chip manufacturing and find the causes of defects, which can help design engineers adjust circuits and layout to reduce the chip manufacturing sensibility to defects, as well as help process engineers adjust process parameters to reduce the quantity and severity of defects. At the same time, in order to gather more information about the chip manufacturing process, the number of test structures in the yield analysis chip increases seriously. So the logic circuits are designed to reduce the number of outside test pins and help analyze the test results.Because of the restriction of EDA platform, the gate-level circuit and the layout of yield analysis chip are designed concurrently. LVS method and post-simulation are studied to resolve yield analysis chip’s special problems. LVS method in this thesis is the combination of traditional Layout Versus Schematic method and formal verification. At the same time, a new tool is developed to generate the simulation netlists for various scale yield analysis chips. The LVS method and post-simulation in this thesis can be well combined with the traditional verification flow. Yield analysis chip is verified under this new verification flow and the experiment results show that the verification process of yield analysis chip is right and stable.