ASIC Backend Design Of Mobile Video Decoder Chip

AVS standard is one audio and video codec standard developed independently by our own country, with characteristics of high compression ratio, low computation and low complexity, etc. The video decoding chip designed by independent technology will enable the local digital products manufacturers out of dependence on foreign companies, but most of the domestic IC design companies are lack of experience in IC backend design field. With the significant reduction of technological size, designing mobile video decoder chip whose characteristics are small size, low power consumption, high speed and low cost will have a stronger market competitiveness.The major work described in this paper is about backend design of AVS mobile video decoding chip using HJTC0.18um CMOS process, which is based on the Synopsys company's technologically advanced ASIC design and verification platform. This paper is made a deep research on the critical theory of in ASIC backend design,such as Logic Synthesis, Formal Verification, Static Timing Analysis, and Layout. Based on the key theory, the chip design flow and optimization programs are proposed, and a backend design of the chip with 320000 gates is completed well. Finally, physical verification is verified the design's layout information without offending design rules and circuit rules.In this design, adding clock gating techniques in the part of the logic synthesis optimization greatly reduce the chip's dynamic power as well as the chip area; in addition, using the primetime tool to do static timing analysis can not only improve the timing closure speed, but also has a very high coverage of timing series analysis;in the chip floor planning stage, the chip is planned by comprehensive consideration of the voltage drop, electromigration, the chip area and so on. Meanwhile, multiple optimizations in placement and routing stage enable the chip's timing with fast convergence speed.