Research And Implementation Of Verification Method For MC-SoC

SoC verification plays a crucial role in discovering errors in chip design and improving the success rate of chip design.As the functions of SoC chips become more and more complex,their design scale is getting larger and larger,and the manufacturing process is more and more advanced,so the requirements for verification in the SoC design process are getting higher and higher.In order to achieve the goal of successful tapingout,it is still impossible to use only software simulation.It is necessary to use a combination of various verification methods.This thesis takes the MC(ModeChangeable)-SoC of the self-developed chip of the teaching and research section as the research object,and studies the function verification method in the SoC design process.The specific work includes the following aspects:1.Research on the functional verification methods widely used in the industry,and propose an overall verification scheme for MC-SoC chips.After completing the system integration work,build a dynamic functional verification platform to perform functional simulation on each module at the system level,which can ensure that each module works normally.In order to improve the efficiency of the entire verification platform,many kind of scripting languages are used to make the verification platform more automated.2.Form verification and static timing analysis of the MC-SoC design.The logic function of the design is ensured by formal verification.The timing of the design is ensured by static timing analysis.The chip can work normally only when both are satisfied.3.Perform layout check consistency check and design rule check on MC-SoC design.Design rule check ensures that the layout data meets the requirements of the foundry for physical rules,ensuring the correctness of the chip manufacturing process,and layout check consistency check ensure that the layout data delivered to the chip foundry is consistent with the functionality defined in the chip specification.4.The inherent software-based dynamic simulation technology has its inherent limitations,which determines that some chip design errors will not be discovered by dynamic function simulation and formal verification,because the speed of simulation cannot be compared with the speed of actual chip operation.But an FPGA system works at a speed close to the real chip system,so that problems in real chip systems can be discovered and solved early.The verification scheme based on this paper has been applied to the verification of MC-SoC chips,and the SoC chip has been successfully taped out.