Research On The Timing Verification For Full-custom Designed VLSI Chip

A timing verification research on the general processor used for communication and network is written in this dissertation. The general processor chip of this paper is integrated by a high-performance PowerPC? RISC microprocessor, a very flexible system integration unit and many communications peripheral controllers. It is a full-custom chip designed in 0.18 micron CMOS technology, containing 5.0 millions transistors with a complex structure. So many factors have to be considered in the timing verification, and the common timing verification methods in the VLSI design can't be done to meet the requirements of the timing verification in such a complex-wide chip. This paper will research on it.By researching into timing verification materials of full-custom designed VLSI chip in VDSM technology and knowledge of static timing analysis, a timing verification plan for the chip is presented in the issue. The classification to the cells is carried on in the chip at first, then more than 10000 kinds of timing measuring templates are wrote. By studying the designed proposal, a tool which is named the"Library Maker"is developed. By using this tool, the cell timing model library which is necessary in static timing analysis is generated. In the end of the paper, an example is given to test the timing verification method tabled in this paper. It shows that the process is feasible and the tools are efficient and practical.