On-chip Op200 System Design, Function And Timing Verification Process

Verification is turning more and more important with SoC s complexity and size increasing. Although current verification flow has covered functional verification and timing verification, by verifying system function points and circuit timing, and EDA foundries have developed many tools to speed up verification works, efficiency of verification is still the main issue of verification works.This thesis studies deeply on SoC verification, including design spec, verification test plan, simulation methodology, static methodology and formal methodology. Based on these, a standardized SoC verification flow is taken out to verify system sufficiently, in which functional verification and timing verification are adopted and verification efficiency is measured by verification quota.The standardized SoC verification flow is used to verify smartcard project OP200. Thesis elaborates the functional verification steps during OP200verification flow, introduces key points of standardized design specification, test plan, verification environment, static verification, formal verification, co-verification and raid prototype system. After evaluation, the coverage rate for RTL code, assertion and functional coverage can reach100%. Thesis also discusses static timing analysis and dynamic timing analysis during OP200verification.We use above verification flow to complete the OP200verification, which successfully tape-out at last, greatly shorten the verification cycle and improve the verification efficiency.