Based On The Soc Encounter Million-gate Asic Back-end Design

Nowadays,with the requirement of greatly shortening time to market (TTM), the semi-custom design based on gate-level has become the mainstream rather than full-custom design. As the critical innovation step of the flow, Back-end design has been a key point in a grand IC company.Issues and challenges have been more and more serious in Deep-Submicron design.1. With the scale enlarge,runtime has sharply increased which lows down the design flow loop efficiency.2. With the critical size shortening,noise interference of interconnection affects not only the quality of signal transition, but also the overall speed and function.3. With the voltage getting low, IR-drop will affect the chip performance directly.4. With the critical size shortening, design for manufacture (DFM) has been a significant factor to yield.This paper researches an ASIC of scale 1.2M gates, frequency 100M Hz and technology node of 0.18um in TSMC, comprehensive and deep discovery and optimization of the back-end flow are proposed:In floorplan stage, IO-driven floorplan is employed which decreases the congestion and improves the timing.In CTS stage, only clock buffers are specified, which decrease the latency and skew.In routing stage, classified routing is adopted, which guarantee the routing quality and decrease the runtime.