Research On Key Techniques For 13-bit 200MSPS Pipelined ADC

High accuracy, high speed analog-to-digital converters(ADCs) are significance building blocks in modern wireless communication systems. The high performance of the wireless communication technology has promoted the development of ADCs towards high precision and high speed. Among various types of ADCs, pipelined ADC can mak a better trade-off between accury, speed, area and power performance. So it is widely used in high speed and high quality wireless communication system, high-definition video signal processing and electromagnetic counterneasure system.The principle of pipelined ADCs is presented in this thesis. The error sources of ADCs are analysed and several improvement approaches are discussed, then the specifications of modules in ADC are derived. The SHA-less architecture is used to reduce the power consumption and minimize the noise, but it could cause some non-ideal effects. Then based on the derivation, the multi-bit first stage could reduce capacotor matching requirement. The first stage is introduced range scaling technology to reduce the matching requirement of capacitor and improve the linearity.Taking into all these factors, the optimization of the complete pipeline system is discussed to minimize the power of ADC. Then the 4-3-3-3-3-2 architecture was chosen for 13-bit pipelined ADC which consists of a 3.5-bit front-end stage followed by four 2.5 bits/stage and the back-end stage is a 2-bit flash Sub-ADC. Finally, detail implementation of the key circuits is presented, including MDAC and Sub-ADC. The first stage circuit was detailly desgined, including a high performance opamp and a low offset dynamic comparator. Their specifications and simulation results are presented with detailed analysis.This thesis designed a 13-bit 200MS/s pipelined ADC circuit based on SMIC 65 nm 1P8M CMOS process and the power supply voltage is 2.5V. The simulation results show that the first stage circuit achieves an SFDR of 93.2d B, an ENOB of 14.52-bit with a 19.3MHz input signal under a 200 MHz sampling frequency and further when s input signal is 80 MHz, the circuit achieves an SFDR of 90.5d B, an ENOB of 14.32-bit. The simulation results of the entire pipelined ADC indicate that when the input signal is 25 MHz and the sampling clock is 200 MHz, the ADC achieves an SFDR of 80.8d B andan ENOB of 12.17-bit.The designed circuit meets requirements of the system.