Research And Design Of High Speed Pipelined ADC

ADC (Analog to Digtial Converter) is the bridge of analog and digital world, whose converting speed and resolution decides the maxium signal frequency and minium signal ampulitude that a system can process respectively. With the rapid spread of 4th generation wirelss communication technology and the development of 5th generation wirelss communication technology, the requriements of ADC’s performance are increasing. Pipelined ADC, which achevies a good compromise between accuracy and speed, has a good propect and research value in wirelss communication and high definition video application.This paper firstly analyses the work principles and struct characters of pipelined ADC, then demonstrates its performance limits and solutions. SHA (sampling and holding amplifer) less technique is used to reduce system noise and power. By taking compare phase forward and matching sample path, we solved the affect causes by SHA less technique. Capacitor scaling technique only between first and second stage not only reduces the load of first stage, but alse keeps circuts afterwards uniform. This paper sets performance index of element circuts and makes a budget of noise power from a system view. In order to improve converting speed, the OTA sets completely in linear way. Folded cascode gain boosting amplifier is designed to satisfy accury and speed requirement. In order to satisfy linearity requirement, a high linearity sampling and holding circuit is designed. Comparator, sub ADC and clock circuits are also designed. Finally, system formed by block circuits is simulated and valided.The 150Ms/s,12-bit ADC is implemented in TSMC 0.18μm 1P6M CMOS process. The supply voltage is 1.8V. The simulation results show that when the ADC is converting at 150Ms/s, its SFDR is 81.6dB. SNDR is 69.5dB. ENOB is 11.3bit. Power of core circuits is 273mW。...