Study Of A High-Speed Pipelined ADC

ABSTRACT:With the rapid development of computer, multimedia, the increase of digitization and integration in semi-conductor technology has considerably promoted the development of analog-digital converter(ADC) technology towards high speed high precision and low power consumption. Among many types of CMOS ADC architectures, the pipelined architectures can achieve good high input frequency dynamic performance and as a high throughput. In order to meet the requirements for ADC in the application, the targeted architecture is a 8bit,200MS/s pipelined analog-to-digital converter.The pipelined ADC consists of the building blocks like sampling-and-hold circuits, sub-ADC, sub-DAC, clock generator and digital correction circuit. To meet the high speed requirement, a dynamic zero-crossing detector and current source to realize a precision charge transfer. It has a simple structure, high speed, small area. The pipelined ADC is followed by seven 1.5-bit stages with a digital correction circuit. In order to ensure the validity of pipelined ADC architecture, system modeling tool---Simulink in Matlab is used to make a system simulation of pipelined ADC before designing of the circuit. The design is based on SMIC 0.18μm CMOS technology under the Cadence design environment, and the power supply is 1.8V.