Research And Key Circuit Design In12-bit High Speed Pipelined ADC

The ADC is the front-end core devices of digital signal processing systemwhich is an essential bridge to connect the digital world and the analog world. Withthe development of the process the power supply voltage reduced, which poses agreat challenge to the high-performance ADC design.A12bit125MSPS Pipelined Video ADC key circuit is designed which is basedon SMIC0.13μm CMOS process. First the thesis analyzes the basic principles ofthe key circuit in pipelined ADC. Then, analyzes the error of the key circuits inpipelined ADC, determines2.5+1.5*7+3with redundant correction pipelinedADC architecture. Finally, designs the key circuits of the system, such as SHAcircuit, the first stage pipelined circuit and the clock circuit.A bootstrap switch circuit with adjustment of the substrate is designed whichmake gate-source voltage of the switch stable. It not only can improve theperformance of the SHA, but also reduce the nonlinear of the sampling switch. Theopamp in pipelined stage is designed by two stages, the first stage uses foldedcascode structure with gain enhancement technology to achieve high gain, thesecond stage uses a common source in order to achieve high output swing. Ahigh-speed, low-jitter clock circuit is designed based on DCS structure, to meet therequirements of high-performance pipelined ADC.The simulation results which simulated by cadence spectre show that whenpower supply voltage is1.2V, the SHA opamp loop gain is102dB, the loopbandwidth is1.18GHz, phase margin is62°, which satisfies the requirement ofprecision of12bits. When the input signal frequency fin is3MHz, the samplingfrequency fs is125MHz, SHA output FFT analysis shows the SNDR is85.7dB,ENOB is13.9bits. The duty ratio of the clock circuit is (50±0.25)%, the rms jitterof the clock signal is148fs.